Texas Instruments
LM3S2671
2024.06.03
ARM Cortex-M3 Stellaris Device
false
8
32
ADC0
Register map for ADC0 peripheral
ADC
0x0
0x0
0x1000
registers
n
ACTSS
ADC Active Sample Sequencer
0x0
-1
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0ACTSS
ADC Active Sample Sequencer
0x0
read-write
n
0x0
0x0
ADC_ACTSS_ASEN0
ADC SS0 Enable
0
1
ADC_ACTSS_ASEN1
ADC SS1 Enable
1
2
ADC_ACTSS_ASEN2
ADC SS2 Enable
2
3
ADC_ACTSS_ASEN3
ADC SS3 Enable
3
4
ADC0EMUX
ADC Event Multiplexer Select
0x14
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
ADC0IM
ADC Interrupt Mask
0x8
read-write
n
0x0
0x0
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ADC0ISC
ADC Interrupt Status and Clear
0xC
read-write
n
0x0
0x0
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
ADC0OSTAT
ADC Overflow Status
0x10
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
ADC0PSSI
ADC Processor Sample Sequence Initiate
0x28
read-write
n
0x0
0x0
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
ADC0RIS
ADC Raw Interrupt Status
0x4
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
ADC0SAC
ADC Sample Averaging Control
0x30
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
ADC0SSCTL0
ADC Sample Sequence Control 0
0x44
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
ADC0SSCTL1
ADC Sample Sequence Control 1
0x64
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL2
ADC Sample Sequence Control 2
0x84
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
ADC0SSCTL3
ADC Sample Sequence Control 3
0xA4
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
ADC0SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
ADC0SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
ADC0SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
ADC0SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
ADC0SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
ADC0SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
ADC0SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
2
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX0_MUX3
4th Sample Input Select
12
14
ADC_SSMUX0_MUX4
5th Sample Input Select
16
18
ADC_SSMUX0_MUX5
6th Sample Input Select
20
22
ADC_SSMUX0_MUX6
7th Sample Input Select
24
26
ADC_SSMUX0_MUX7
8th Sample Input Select
28
30
ADC0SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
2
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX1_MUX3
4th Sample Input Select
12
14
ADC0SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
2
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX2_MUX3
4th Sample Input Select
12
14
ADC0SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
2
ADC0SSPRI
ADC Sample Sequencer Priority
0x20
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
ADC0USTAT
ADC Underflow Status
0x18
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
EMUX
ADC Event Multiplexer Select
0x14
-1
read-write
n
0x0
0x0
ADC_EMUX_EM0
SS0 Trigger Select
0
4
ADC_EMUX_EM0_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM0_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM0_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM0_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM0_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM0_TIMER
Timer
0x5
ADC_EMUX_EM0_PWM0
PWM0
0x6
ADC_EMUX_EM0_PWM1
PWM1
0x7
ADC_EMUX_EM0_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM1
SS1 Trigger Select
4
8
ADC_EMUX_EM1_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM1_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM1_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM1_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM1_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM1_TIMER
Timer
0x5
ADC_EMUX_EM1_PWM0
PWM0
0x6
ADC_EMUX_EM1_PWM1
PWM1
0x7
ADC_EMUX_EM1_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM2
SS2 Trigger Select
8
12
ADC_EMUX_EM2_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM2_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM2_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM2_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM2_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM2_TIMER
Timer
0x5
ADC_EMUX_EM2_PWM0
PWM0
0x6
ADC_EMUX_EM2_PWM1
PWM1
0x7
ADC_EMUX_EM2_ALWAYS
Always (continuously sample)
0xf
ADC_EMUX_EM3
SS3 Trigger Select
12
16
ADC_EMUX_EM3_PROCESSOR
Processor (default)
0x0
ADC_EMUX_EM3_COMP0
Analog Comparator 0
0x1
ADC_EMUX_EM3_COMP1
Analog Comparator 1
0x2
ADC_EMUX_EM3_COMP2
Analog Comparator 2
0x3
ADC_EMUX_EM3_EXTERNAL
External (GPIO PB4)
0x4
ADC_EMUX_EM3_TIMER
Timer
0x5
ADC_EMUX_EM3_PWM0
PWM0
0x6
ADC_EMUX_EM3_PWM1
PWM1
0x7
ADC_EMUX_EM3_ALWAYS
Always (continuously sample)
0xf
IM
ADC Interrupt Mask
0x8
-1
read-write
n
0x0
0x0
ADC_IM_MASK0
SS0 Interrupt Mask
0
1
ADC_IM_MASK1
SS1 Interrupt Mask
1
2
ADC_IM_MASK2
SS2 Interrupt Mask
2
3
ADC_IM_MASK3
SS3 Interrupt Mask
3
4
ISC
ADC Interrupt Status and Clear
0xC
-1
read-write
n
0x0
0x0
ADC_ISC_IN0
SS0 Interrupt Status and Clear
0
1
ADC_ISC_IN1
SS1 Interrupt Status and Clear
1
2
ADC_ISC_IN2
SS2 Interrupt Status and Clear
2
3
ADC_ISC_IN3
SS3 Interrupt Status and Clear
3
4
OSTAT
ADC Overflow Status
0x10
-1
read-write
n
0x0
0x0
ADC_OSTAT_OV0
SS0 FIFO Overflow
0
1
ADC_OSTAT_OV1
SS1 FIFO Overflow
1
2
ADC_OSTAT_OV2
SS2 FIFO Overflow
2
3
ADC_OSTAT_OV3
SS3 FIFO Overflow
3
4
PSSI
ADC Processor Sample Sequence Initiate
0x28
-1
read-write
n
0x0
0x0
ADC_PSSI_SS0
SS0 Initiate
0
1
ADC_PSSI_SS1
SS1 Initiate
1
2
ADC_PSSI_SS2
SS2 Initiate
2
3
ADC_PSSI_SS3
SS3 Initiate
3
4
RIS
ADC Raw Interrupt Status
0x4
-1
read-write
n
0x0
0x0
ADC_RIS_INR0
SS0 Raw Interrupt Status
0
1
ADC_RIS_INR1
SS1 Raw Interrupt Status
1
2
ADC_RIS_INR2
SS2 Raw Interrupt Status
2
3
ADC_RIS_INR3
SS3 Raw Interrupt Status
3
4
SAC
ADC Sample Averaging Control
0x30
-1
read-write
n
0x0
0x0
ADC_SAC_AVG
Hardware Averaging Control
0
3
ADC_SAC_AVG_OFF
No hardware oversampling
0x0
ADC_SAC_AVG_2X
2x hardware oversampling
0x1
ADC_SAC_AVG_4X
4x hardware oversampling
0x2
ADC_SAC_AVG_8X
8x hardware oversampling
0x3
ADC_SAC_AVG_16X
16x hardware oversampling
0x4
ADC_SAC_AVG_32X
32x hardware oversampling
0x5
ADC_SAC_AVG_64X
64x hardware oversampling
0x6
SSCTL0
ADC Sample Sequence Control 0
0x44
-1
read-write
n
0x0
0x0
ADC_SSCTL0_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL0_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL0_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL0_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL0_D4
5th Sample Diff Input Select
16
17
ADC_SSCTL0_D5
6th Sample Diff Input Select
20
21
ADC_SSCTL0_D6
7th Sample Diff Input Select
24
25
ADC_SSCTL0_D7
8th Sample Diff Input Select
28
29
ADC_SSCTL0_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL0_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL0_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL0_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL0_END4
5th Sample is End of Sequence
17
18
ADC_SSCTL0_END5
6th Sample is End of Sequence
21
22
ADC_SSCTL0_END6
7th Sample is End of Sequence
25
26
ADC_SSCTL0_END7
8th Sample is End of Sequence
29
30
ADC_SSCTL0_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL0_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL0_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL0_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL0_IE4
5th Sample Interrupt Enable
18
19
ADC_SSCTL0_IE5
6th Sample Interrupt Enable
22
23
ADC_SSCTL0_IE6
7th Sample Interrupt Enable
26
27
ADC_SSCTL0_IE7
8th Sample Interrupt Enable
30
31
ADC_SSCTL0_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL0_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL0_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL0_TS3
4th Sample Temp Sensor Select
15
16
ADC_SSCTL0_TS4
5th Sample Temp Sensor Select
19
20
ADC_SSCTL0_TS5
6th Sample Temp Sensor Select
23
24
ADC_SSCTL0_TS6
7th Sample Temp Sensor Select
27
28
ADC_SSCTL0_TS7
8th Sample Temp Sensor Select
31
32
SSCTL1
ADC Sample Sequence Control 1
0x64
-1
read-write
n
0x0
0x0
ADC_SSCTL1_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL1_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL1_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL1_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL1_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL1_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL1_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL1_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL1_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL1_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL1_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL1_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL1_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL1_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL1_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL1_TS3
4th Sample Temp Sensor Select
15
16
SSCTL2
ADC Sample Sequence Control 2
0x84
-1
read-write
n
0x0
0x0
ADC_SSCTL2_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL2_D1
2nd Sample Diff Input Select
4
5
ADC_SSCTL2_D2
3rd Sample Diff Input Select
8
9
ADC_SSCTL2_D3
4th Sample Diff Input Select
12
13
ADC_SSCTL2_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL2_END1
2nd Sample is End of Sequence
5
6
ADC_SSCTL2_END2
3rd Sample is End of Sequence
9
10
ADC_SSCTL2_END3
4th Sample is End of Sequence
13
14
ADC_SSCTL2_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL2_IE1
2nd Sample Interrupt Enable
6
7
ADC_SSCTL2_IE2
3rd Sample Interrupt Enable
10
11
ADC_SSCTL2_IE3
4th Sample Interrupt Enable
14
15
ADC_SSCTL2_TS0
1st Sample Temp Sensor Select
3
4
ADC_SSCTL2_TS1
2nd Sample Temp Sensor Select
7
8
ADC_SSCTL2_TS2
3rd Sample Temp Sensor Select
11
12
ADC_SSCTL2_TS3
4th Sample Temp Sensor Select
15
16
SSCTL3
ADC Sample Sequence Control 3
0xA4
-1
read-write
n
0x0
0x0
ADC_SSCTL3_D0
1st Sample Diff Input Select
0
1
ADC_SSCTL3_END0
1st Sample is End of Sequence
1
2
ADC_SSCTL3_IE0
1st Sample Interrupt Enable
2
3
ADC_SSCTL3_TS0
1st Sample Temp Sensor Select
3
4
SSFIFO0
ADC Sample Sequence Result FIFO 0
0x48
-1
read-write
n
0x0
0x0
ADC_SSFIFO0_DATA
Conversion Result Data
0
10
SSFIFO1
ADC Sample Sequence Result FIFO 1
0x68
-1
read-write
n
0x0
0x0
ADC_SSFIFO1_DATA
Conversion Result Data
0
10
SSFIFO2
ADC Sample Sequence Result FIFO 2
0x88
-1
read-write
n
0x0
0x0
ADC_SSFIFO2_DATA
Conversion Result Data
0
10
SSFIFO3
ADC Sample Sequence Result FIFO 3
0xA8
-1
read-write
n
0x0
0x0
ADC_SSFIFO3_DATA
Conversion Result Data
0
10
SSFSTAT0
ADC Sample Sequence FIFO 0 Status
0x4C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT0_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT0_FULL
FIFO Full
12
13
ADC_SSFSTAT0_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT0_TPTR
FIFO Tail Pointer
0
4
SSFSTAT1
ADC Sample Sequence FIFO 1 Status
0x6C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT1_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT1_FULL
FIFO Full
12
13
ADC_SSFSTAT1_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT1_TPTR
FIFO Tail Pointer
0
4
SSFSTAT2
ADC Sample Sequence FIFO 2 Status
0x8C
-1
read-write
n
0x0
0x0
ADC_SSFSTAT2_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT2_FULL
FIFO Full
12
13
ADC_SSFSTAT2_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT2_TPTR
FIFO Tail Pointer
0
4
SSFSTAT3
ADC Sample Sequence FIFO 3 Status
0xAC
-1
read-write
n
0x0
0x0
ADC_SSFSTAT3_EMPTY
FIFO Empty
8
9
ADC_SSFSTAT3_FULL
FIFO Full
12
13
ADC_SSFSTAT3_HPTR
FIFO Head Pointer
4
8
ADC_SSFSTAT3_TPTR
FIFO Tail Pointer
0
4
SSMUX0
ADC Sample Sequence Input Multiplexer Select 0
0x40
-1
read-write
n
0x0
0x0
ADC_SSMUX0_MUX0
1st Sample Input Select
0
2
ADC_SSMUX0_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX0_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX0_MUX3
4th Sample Input Select
12
14
ADC_SSMUX0_MUX4
5th Sample Input Select
16
18
ADC_SSMUX0_MUX5
6th Sample Input Select
20
22
ADC_SSMUX0_MUX6
7th Sample Input Select
24
26
ADC_SSMUX0_MUX7
8th Sample Input Select
28
30
SSMUX1
ADC Sample Sequence Input Multiplexer Select 1
0x60
-1
read-write
n
0x0
0x0
ADC_SSMUX1_MUX0
1st Sample Input Select
0
2
ADC_SSMUX1_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX1_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX1_MUX3
4th Sample Input Select
12
14
SSMUX2
ADC Sample Sequence Input Multiplexer Select 2
0x80
-1
read-write
n
0x0
0x0
ADC_SSMUX2_MUX0
1st Sample Input Select
0
2
ADC_SSMUX2_MUX1
2nd Sample Input Select
4
6
ADC_SSMUX2_MUX2
3rd Sample Input Select
8
10
ADC_SSMUX2_MUX3
4th Sample Input Select
12
14
SSMUX3
ADC Sample Sequence Input Multiplexer Select 3
0xA0
-1
read-write
n
0x0
0x0
ADC_SSMUX3_MUX0
1st Sample Input Select
0
2
SSPRI
ADC Sample Sequencer Priority
0x20
-1
read-write
n
0x0
0x0
ADC_SSPRI_SS0
SS0 Priority
0
2
ADC_SSPRI_SS0_1ST
First priority
0x0
ADC_SSPRI_SS0_2ND
Second priority
0x1
ADC_SSPRI_SS0_3RD
Third priority
0x2
ADC_SSPRI_SS0_4TH
Fourth priority
0x3
ADC_SSPRI_SS1
SS1 Priority
4
6
ADC_SSPRI_SS1_1ST
First priority
0x0
ADC_SSPRI_SS1_2ND
Second priority
0x1
ADC_SSPRI_SS1_3RD
Third priority
0x2
ADC_SSPRI_SS1_4TH
Fourth priority
0x3
ADC_SSPRI_SS2
SS2 Priority
8
10
ADC_SSPRI_SS2_1ST
First priority
0x0
ADC_SSPRI_SS2_2ND
Second priority
0x1
ADC_SSPRI_SS2_3RD
Third priority
0x2
ADC_SSPRI_SS2_4TH
Fourth priority
0x3
ADC_SSPRI_SS3
SS3 Priority
12
14
ADC_SSPRI_SS3_1ST
First priority
0x0
ADC_SSPRI_SS3_2ND
Second priority
0x1
ADC_SSPRI_SS3_3RD
Third priority
0x2
ADC_SSPRI_SS3_4TH
Fourth priority
0x3
USTAT
ADC Underflow Status
0x18
-1
read-write
n
0x0
0x0
ADC_USTAT_UV0
SS0 FIFO Underflow
0
1
ADC_USTAT_UV1
SS1 FIFO Underflow
1
2
ADC_USTAT_UV2
SS2 FIFO Underflow
2
3
ADC_USTAT_UV3
SS3 FIFO Underflow
3
4
CAN0
Register map for CAN0 peripheral
CAN
0x0
0x0
0x1000
registers
n
BIT
CAN Bit Timing
0xC
-1
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
BRPE
CAN Baud Rate Prescaler Extension
0x18
-1
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0BIT
CAN Bit Timing
0xC
read-write
n
0x0
0x0
CAN_BIT_BRP
Baud Rate Prescaler
0
6
CAN_BIT_SJW
(Re)Synchronization Jump Width
6
8
CAN_BIT_TSEG1
Time Segment Before Sample Point
8
12
CAN_BIT_TSEG2
Time Segment after Sample Point
12
15
CAN0BRPE
CAN Baud Rate Prescaler Extension
0x18
read-write
n
0x0
0x0
CAN_BRPE_BRPE
Baud Rate Prescaler Extension
0
4
CAN0CTL
CAN Control
0x0
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
CAN0ERR
CAN Error Counter
0x8
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
CAN0IF1ARB1
CAN IF1 Arbitration 1
0x30
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
CAN0IF1ARB2
CAN IF1 Arbitration 2
0x34
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
CAN0IF1CMSK
CAN IF1 Command Mask
0x24
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
CAN0IF1CRQ
CAN IF1 Command Request
0x20
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF1DA1
CAN IF1 Data A1
0x3C
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
CAN0IF1DA2
CAN IF1 Data A2
0x40
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
CAN0IF1DB1
CAN IF1 Data B1
0x44
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
CAN0IF1DB2
CAN IF1 Data B2
0x48
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
CAN0IF1MCTL
CAN IF1 Message Control
0x38
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF1MSK1
CAN IF1 Mask 1
0x28
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
CAN0IF1MSK2
CAN IF1 Mask 2
0x2C
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
CAN0IF2ARB1
CAN IF2 Arbitration 1
0x90
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
CAN0IF2ARB2
CAN IF2 Arbitration 2
0x94
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
CAN0IF2CMSK
CAN IF2 Command Mask
0x84
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
CAN0IF2CRQ
CAN IF2 Command Request
0x80
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number; it is interpreted as 0x20, or object 32
0x0
CAN0IF2DA1
CAN IF2 Data A1
0x9C
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
CAN0IF2DA2
CAN IF2 Data A2
0xA0
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
CAN0IF2DB1
CAN IF2 Data B1
0xA4
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
CAN0IF2DB2
CAN IF2 Data B2
0xA8
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
CAN0IF2MCTL
CAN IF2 Message Control
0x98
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
CAN0IF2MSK1
CAN IF2 Mask 1
0x88
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
CAN0IF2MSK2
CAN IF2 Mask 2
0x8C
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
CAN0INT
CAN Interrupt
0x10
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
CAN0MSG1INT
CAN Message 1 Interrupt Pending
0x140
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG1VAL
CAN Message 1 Valid
0x160
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
CAN0MSG2INT
CAN Message 2 Interrupt Pending
0x144
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
CAN0MSG2VAL
CAN Message 2 Valid
0x164
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
CAN0NWDA1
CAN New Data 1
0x120
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
CAN0NWDA2
CAN New Data 2
0x124
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
CAN0STS
CAN Status
0x4
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
CAN0TST
CAN Test
0x14
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
CAN0TXRQ1
CAN Transmission Request 1
0x100
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
CAN0TXRQ2
CAN Transmission Request 2
0x104
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
CTL
CAN Control
0x0
-1
read-write
n
0x0
0x0
CAN_CTL_CCE
Configuration Change Enable
6
7
CAN_CTL_DAR
Disable Automatic-Retransmission
5
6
CAN_CTL_EIE
Error Interrupt Enable
3
4
CAN_CTL_IE
CAN Interrupt Enable
1
2
CAN_CTL_INIT
Initialization
0
1
CAN_CTL_SIE
Status Interrupt Enable
2
3
CAN_CTL_TEST
Test Mode Enable
7
8
ERR
CAN Error Counter
0x8
-1
read-write
n
0x0
0x0
CAN_ERR_REC
Receive Error Counter
8
15
CAN_ERR_RP
Received Error Passive
15
16
CAN_ERR_TEC
Transmit Error Counter
0
8
IF1ARB1
CAN IF1 Arbitration 1
0x30
-1
read-write
n
0x0
0x0
CAN_IF1ARB1_ID
Message Identifier
0
16
IF1ARB2
CAN IF1 Arbitration 2
0x34
-1
read-write
n
0x0
0x0
CAN_IF1ARB2_DIR
Message Direction
13
14
CAN_IF1ARB2_ID
Message Identifier
0
13
CAN_IF1ARB2_MSGVAL
Message Valid
15
16
CAN_IF1ARB2_XTD
Extended Identifier
14
15
IF1CMSK
CAN IF1 Command Mask
0x24
-1
read-write
n
0x0
0x0
CAN_IF1CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF1CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF1CMSK_CONTROL
Access Control Bits
4
5
CAN_IF1CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF1CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF1CMSK_MASK
Access Mask Bits
6
7
CAN_IF1CMSK_NEWDAT
Access New Data
2
3
CAN_IF1CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF1CMSK_WRNRD
Write, Not Read
7
8
IF1CRQ
CAN IF1 Command Request
0x20
-1
read-write
n
0x0
0x0
CAN_IF1CRQ_BUSY
Busy Flag
15
16
CAN_IF1CRQ_MNUM
Message Number
0
6
CAN_IF1CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF1DA1
CAN IF1 Data A1
0x3C
-1
read-write
n
0x0
0x0
CAN_IF1DA1_DATA
Data
0
16
IF1DA2
CAN IF1 Data A2
0x40
-1
read-write
n
0x0
0x0
CAN_IF1DA2_DATA
Data
0
16
IF1DB1
CAN IF1 Data B1
0x44
-1
read-write
n
0x0
0x0
CAN_IF1DB1_DATA
Data
0
16
IF1DB2
CAN IF1 Data B2
0x48
-1
read-write
n
0x0
0x0
CAN_IF1DB2_DATA
Data
0
16
IF1MCTL
CAN IF1 Message Control
0x38
-1
read-write
n
0x0
0x0
CAN_IF1MCTL_DLC
Data Length Code
0
4
CAN_IF1MCTL_EOB
End of Buffer
7
8
CAN_IF1MCTL_INTPND
Interrupt Pending
13
14
CAN_IF1MCTL_MSGLST
Message Lost
14
15
CAN_IF1MCTL_NEWDAT
New Data
15
16
CAN_IF1MCTL_RMTEN
Remote Enable
9
10
CAN_IF1MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF1MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF1MCTL_TXRQST
Transmit Request
8
9
CAN_IF1MCTL_UMASK
Use Acceptance Mask
12
13
IF1MSK1
CAN IF1 Mask 1
0x28
-1
read-write
n
0x0
0x0
CAN_IF1MSK1_IDMSK
Identifier Mask
0
16
IF1MSK2
CAN IF1 Mask 2
0x2C
-1
read-write
n
0x0
0x0
CAN_IF1MSK2_IDMSK
Identifier Mask
0
13
CAN_IF1MSK2_MDIR
Mask Message Direction
14
15
CAN_IF1MSK2_MXTD
Mask Extended Identifier
15
16
IF2ARB1
CAN IF2 Arbitration 1
0x90
-1
read-write
n
0x0
0x0
CAN_IF2ARB1_ID
Message Identifier
0
16
IF2ARB2
CAN IF2 Arbitration 2
0x94
-1
read-write
n
0x0
0x0
CAN_IF2ARB2_DIR
Message Direction
13
14
CAN_IF2ARB2_ID
Message Identifier
0
13
CAN_IF2ARB2_MSGVAL
Message Valid
15
16
CAN_IF2ARB2_XTD
Extended Identifier
14
15
IF2CMSK
CAN IF2 Command Mask
0x84
-1
read-write
n
0x0
0x0
CAN_IF2CMSK_ARB
Access Arbitration Bits
5
6
CAN_IF2CMSK_CLRINTPND
Clear Interrupt Pending Bit
3
4
CAN_IF2CMSK_CONTROL
Access Control Bits
4
5
CAN_IF2CMSK_DATAA
Access Data Byte 0 to 3
1
2
CAN_IF2CMSK_DATAB
Access Data Byte 4 to 7
0
1
CAN_IF2CMSK_MASK
Access Mask Bits
6
7
CAN_IF2CMSK_NEWDAT
Access New Data
2
3
CAN_IF2CMSK_TXRQST
Access Transmission Request
2
3
CAN_IF2CMSK_WRNRD
Write, Not Read
7
8
IF2CRQ
CAN IF2 Command Request
0x80
-1
read-write
n
0x0
0x0
CAN_IF2CRQ_BUSY
Busy Flag
15
16
CAN_IF2CRQ_MNUM
Message Number
0
6
CAN_IF2CRQ_MNUM_RSVD
0 is not a valid message number it is interpreted as 0x20, or object 32
0x0
IF2DA1
CAN IF2 Data A1
0x9C
-1
read-write
n
0x0
0x0
CAN_IF2DA1_DATA
Data
0
16
IF2DA2
CAN IF2 Data A2
0xA0
-1
read-write
n
0x0
0x0
CAN_IF2DA2_DATA
Data
0
16
IF2DB1
CAN IF2 Data B1
0xA4
-1
read-write
n
0x0
0x0
CAN_IF2DB1_DATA
Data
0
16
IF2DB2
CAN IF2 Data B2
0xA8
-1
read-write
n
0x0
0x0
CAN_IF2DB2_DATA
Data
0
16
IF2MCTL
CAN IF2 Message Control
0x98
-1
read-write
n
0x0
0x0
CAN_IF2MCTL_DLC
Data Length Code
0
4
CAN_IF2MCTL_EOB
End of Buffer
7
8
CAN_IF2MCTL_INTPND
Interrupt Pending
13
14
CAN_IF2MCTL_MSGLST
Message Lost
14
15
CAN_IF2MCTL_NEWDAT
New Data
15
16
CAN_IF2MCTL_RMTEN
Remote Enable
9
10
CAN_IF2MCTL_RXIE
Receive Interrupt Enable
10
11
CAN_IF2MCTL_TXIE
Transmit Interrupt Enable
11
12
CAN_IF2MCTL_TXRQST
Transmit Request
8
9
CAN_IF2MCTL_UMASK
Use Acceptance Mask
12
13
IF2MSK1
CAN IF2 Mask 1
0x88
-1
read-write
n
0x0
0x0
CAN_IF2MSK1_IDMSK
Identifier Mask
0
16
IF2MSK2
CAN IF2 Mask 2
0x8C
-1
read-write
n
0x0
0x0
CAN_IF2MSK2_IDMSK
Identifier Mask
0
13
CAN_IF2MSK2_MDIR
Mask Message Direction
14
15
CAN_IF2MSK2_MXTD
Mask Extended Identifier
15
16
INT
CAN Interrupt
0x10
-1
read-write
n
0x0
0x0
CAN_INT_INTID
Interrupt Identifier
0
16
CAN_INT_INTID_NONE
No interrupt pending
0x0
CAN_INT_INTID_STATUS
Status Interrupt
0x8000
MSG1INT
CAN Message 1 Interrupt Pending
0x140
-1
read-write
n
0x0
0x0
CAN_MSG1INT_INTPND
Interrupt Pending Bits
0
16
MSG1VAL
CAN Message 1 Valid
0x160
-1
read-write
n
0x0
0x0
CAN_MSG1VAL_MSGVAL
Message Valid Bits
0
16
MSG2INT
CAN Message 2 Interrupt Pending
0x144
-1
read-write
n
0x0
0x0
CAN_MSG2INT_INTPND
Interrupt Pending Bits
0
16
MSG2VAL
CAN Message 2 Valid
0x164
-1
read-write
n
0x0
0x0
CAN_MSG2VAL_MSGVAL
Message Valid Bits
0
16
NWDA1
CAN New Data 1
0x120
-1
read-write
n
0x0
0x0
CAN_NWDA1_NEWDAT
New Data Bits
0
16
NWDA2
CAN New Data 2
0x124
-1
read-write
n
0x0
0x0
CAN_NWDA2_NEWDAT
New Data Bits
0
16
STS
CAN Status
0x4
-1
read-write
n
0x0
0x0
CAN_STS_BOFF
Bus-Off Status
7
8
CAN_STS_EPASS
Error Passive
5
6
CAN_STS_EWARN
Warning Status
6
7
CAN_STS_LEC
Last Error Code
0
3
CAN_STS_LEC_NONE
No Error
0x0
CAN_STS_LEC_STUFF
Stuff Error
0x1
CAN_STS_LEC_FORM
Format Error
0x2
CAN_STS_LEC_ACK
ACK Error
0x3
CAN_STS_LEC_BIT1
Bit 1 Error
0x4
CAN_STS_LEC_BIT0
Bit 0 Error
0x5
CAN_STS_LEC_CRC
CRC Error
0x6
CAN_STS_LEC_NOEVENT
No Event
0x7
CAN_STS_RXOK
Received a Message Successfully
4
5
CAN_STS_TXOK
Transmitted a Message Successfully
3
4
TST
CAN Test
0x14
-1
read-write
n
0x0
0x0
CAN_TST_BASIC
Basic Mode
2
3
CAN_TST_LBACK
Loopback Mode
4
5
CAN_TST_RX
Receive Observation
7
8
CAN_TST_SILENT
Silent Mode
3
4
CAN_TST_TX
Transmit Control
5
7
CAN_TST_TX_CANCTL
CAN Module Control
0x0
CAN_TST_TX_SAMPLE
Sample Point
0x1
CAN_TST_TX_DOMINANT
Driven Low
0x2
CAN_TST_TX_RECESSIVE
Driven High
0x3
TXRQ1
CAN Transmission Request 1
0x100
-1
read-write
n
0x0
0x0
CAN_TXRQ1_TXRQST
Transmission Request Bits
0
16
TXRQ2
CAN Transmission Request 2
0x104
-1
read-write
n
0x0
0x0
CAN_TXRQ2_TXRQST
Transmission Request Bits
0
16
COMP
Register map for COMP peripheral
COMP
0x0
0x0
0x1000
registers
n
ACCTL0
Analog Comparator Control 0
0x24
-1
read-write
n
0x0
0x0
COMP_ACCTL0_ASRCP
Analog Source Positive
9
11
COMP_ACCTL0_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL0_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL0_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL0_CINV
Comparator Output Invert
1
2
COMP_ACCTL0_ISEN
Interrupt Sense
2
4
COMP_ACCTL0_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL0_ISEN_FALL
Falling edge
0x1
COMP_ACCTL0_ISEN_RISE
Rising edge
0x2
COMP_ACCTL0_ISEN_BOTH
Either edge
0x3
COMP_ACCTL0_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL0_TOEN
Trigger Output Enable
11
12
COMP_ACCTL0_TSEN
Trigger Sense
5
7
COMP_ACCTL0_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL0_TSEN_FALL
Falling edge
0x1
COMP_ACCTL0_TSEN_RISE
Rising edge
0x2
COMP_ACCTL0_TSEN_BOTH
Either edge
0x3
COMP_ACCTL0_TSLVAL
Trigger Sense Level Value
7
8
ACCTL1
Analog Comparator Control 1
0x44
-1
read-write
n
0x0
0x0
COMP_ACCTL1_ASRCP
Analog Source Positive
9
11
COMP_ACCTL1_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL1_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL1_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL1_CINV
Comparator Output Invert
1
2
COMP_ACCTL1_ISEN
Interrupt Sense
2
4
COMP_ACCTL1_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL1_ISEN_FALL
Falling edge
0x1
COMP_ACCTL1_ISEN_RISE
Rising edge
0x2
COMP_ACCTL1_ISEN_BOTH
Either edge
0x3
COMP_ACCTL1_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL1_TOEN
Trigger Output Enable
11
12
COMP_ACCTL1_TSEN
Trigger Sense
5
7
COMP_ACCTL1_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL1_TSEN_FALL
Falling edge
0x1
COMP_ACCTL1_TSEN_RISE
Rising edge
0x2
COMP_ACCTL1_TSEN_BOTH
Either edge
0x3
COMP_ACCTL1_TSLVAL
Trigger Sense Level Value
7
8
ACCTL2
Analog Comparator Control 2
0x64
-1
read-write
n
0x0
0x0
COMP_ACCTL2_ASRCP
Analog Source Positive
9
11
COMP_ACCTL2_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL2_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL2_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL2_CINV
Comparator Output Invert
1
2
COMP_ACCTL2_ISEN
Interrupt Sense
2
4
COMP_ACCTL2_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL2_ISEN_FALL
Falling edge
0x1
COMP_ACCTL2_ISEN_RISE
Rising edge
0x2
COMP_ACCTL2_ISEN_BOTH
Either edge
0x3
COMP_ACCTL2_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL2_TOEN
Trigger Output Enable
11
12
COMP_ACCTL2_TSEN
Trigger Sense
5
7
COMP_ACCTL2_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL2_TSEN_FALL
Falling edge
0x1
COMP_ACCTL2_TSEN_RISE
Rising edge
0x2
COMP_ACCTL2_TSEN_BOTH
Either edge
0x3
COMP_ACCTL2_TSLVAL
Trigger Sense Level Value
7
8
ACINTEN
Analog Comparator Interrupt Enable
0x8
-1
read-write
n
0x0
0x0
COMP_ACINTEN_IN0
Comparator 0 Interrupt Enable
0
1
COMP_ACINTEN_IN1
Comparator 1 Interrupt Enable
1
2
COMP_ACINTEN_IN2
Comparator 2 Interrupt Enable
2
3
ACMIS
Analog Comparator Masked Interrupt Status
0x0
-1
read-write
n
0x0
0x0
COMP_ACMIS_IN0
Comparator 0 Masked Interrupt Status
0
1
COMP_ACMIS_IN1
Comparator 1 Masked Interrupt Status
1
2
COMP_ACMIS_IN2
Comparator 2 Masked Interrupt Status
2
3
ACREFCTL
Analog Comparator Reference Voltage Control
0x10
-1
read-write
n
0x0
0x0
COMP_ACREFCTL_EN
Resistor Ladder Enable
9
10
COMP_ACREFCTL_RNG
Resistor Ladder Range
8
9
COMP_ACREFCTL_VREF
Resistor Ladder Voltage Ref
0
4
ACRIS
Analog Comparator Raw Interrupt Status
0x4
-1
read-write
n
0x0
0x0
COMP_ACRIS_IN0
Comparator 0 Interrupt Status
0
1
COMP_ACRIS_IN1
Comparator 1 Interrupt Status
1
2
COMP_ACRIS_IN2
Comparator 2 Interrupt Status
2
3
ACSTAT0
Analog Comparator Status 0
0x20
-1
read-write
n
0x0
0x0
COMP_ACSTAT0_OVAL
Comparator Output Value
1
2
ACSTAT1
Analog Comparator Status 1
0x40
-1
read-write
n
0x0
0x0
COMP_ACSTAT1_OVAL
Comparator Output Value
1
2
ACSTAT2
Analog Comparator Status 2
0x60
-1
read-write
n
0x0
0x0
COMP_ACSTAT2_OVAL
Comparator Output Value
1
2
COMPACCTL0
Analog Comparator Control 0
0x24
read-write
n
0x0
0x0
COMP_ACCTL0_ASRCP
Analog Source Positive
9
11
COMP_ACCTL0_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL0_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL0_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL0_CINV
Comparator Output Invert
1
2
COMP_ACCTL0_ISEN
Interrupt Sense
2
4
COMP_ACCTL0_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL0_ISEN_FALL
Falling edge
0x1
COMP_ACCTL0_ISEN_RISE
Rising edge
0x2
COMP_ACCTL0_ISEN_BOTH
Either edge
0x3
COMP_ACCTL0_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL0_TOEN
Trigger Output Enable
11
12
COMP_ACCTL0_TSEN
Trigger Sense
5
7
COMP_ACCTL0_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL0_TSEN_FALL
Falling edge
0x1
COMP_ACCTL0_TSEN_RISE
Rising edge
0x2
COMP_ACCTL0_TSEN_BOTH
Either edge
0x3
COMP_ACCTL0_TSLVAL
Trigger Sense Level Value
7
8
COMPACCTL1
Analog Comparator Control 1
0x44
read-write
n
0x0
0x0
COMP_ACCTL1_ASRCP
Analog Source Positive
9
11
COMP_ACCTL1_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL1_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL1_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL1_CINV
Comparator Output Invert
1
2
COMP_ACCTL1_ISEN
Interrupt Sense
2
4
COMP_ACCTL1_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL1_ISEN_FALL
Falling edge
0x1
COMP_ACCTL1_ISEN_RISE
Rising edge
0x2
COMP_ACCTL1_ISEN_BOTH
Either edge
0x3
COMP_ACCTL1_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL1_TOEN
Trigger Output Enable
11
12
COMP_ACCTL1_TSEN
Trigger Sense
5
7
COMP_ACCTL1_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL1_TSEN_FALL
Falling edge
0x1
COMP_ACCTL1_TSEN_RISE
Rising edge
0x2
COMP_ACCTL1_TSEN_BOTH
Either edge
0x3
COMP_ACCTL1_TSLVAL
Trigger Sense Level Value
7
8
COMPACCTL2
Analog Comparator Control 2
0x64
read-write
n
0x0
0x0
COMP_ACCTL2_ASRCP
Analog Source Positive
9
11
COMP_ACCTL2_ASRCP_PIN
Pin value of Cn+
0x0
COMP_ACCTL2_ASRCP_PIN0
Pin value of C0+
0x1
COMP_ACCTL2_ASRCP_REF
Internal voltage reference (VIREF)
0x2
COMP_ACCTL2_CINV
Comparator Output Invert
1
2
COMP_ACCTL2_ISEN
Interrupt Sense
2
4
COMP_ACCTL2_ISEN_LEVEL
Level sense, see ISLVAL
0x0
COMP_ACCTL2_ISEN_FALL
Falling edge
0x1
COMP_ACCTL2_ISEN_RISE
Rising edge
0x2
COMP_ACCTL2_ISEN_BOTH
Either edge
0x3
COMP_ACCTL2_ISLVAL
Interrupt Sense Level Value
4
5
COMP_ACCTL2_TOEN
Trigger Output Enable
11
12
COMP_ACCTL2_TSEN
Trigger Sense
5
7
COMP_ACCTL2_TSEN_LEVEL
Level sense, see TSLVAL
0x0
COMP_ACCTL2_TSEN_FALL
Falling edge
0x1
COMP_ACCTL2_TSEN_RISE
Rising edge
0x2
COMP_ACCTL2_TSEN_BOTH
Either edge
0x3
COMP_ACCTL2_TSLVAL
Trigger Sense Level Value
7
8
COMPACINTEN
Analog Comparator Interrupt Enable
0x8
read-write
n
0x0
0x0
COMP_ACINTEN_IN0
Comparator 0 Interrupt Enable
0
1
COMP_ACINTEN_IN1
Comparator 1 Interrupt Enable
1
2
COMP_ACINTEN_IN2
Comparator 2 Interrupt Enable
2
3
COMPACMIS
Analog Comparator Masked Interrupt Status
0x0
read-write
n
0x0
0x0
COMP_ACMIS_IN0
Comparator 0 Masked Interrupt Status
0
1
COMP_ACMIS_IN1
Comparator 1 Masked Interrupt Status
1
2
COMP_ACMIS_IN2
Comparator 2 Masked Interrupt Status
2
3
COMPACREFCTL
Analog Comparator Reference Voltage Control
0x10
read-write
n
0x0
0x0
COMP_ACREFCTL_EN
Resistor Ladder Enable
9
10
COMP_ACREFCTL_RNG
Resistor Ladder Range
8
9
COMP_ACREFCTL_VREF
Resistor Ladder Voltage Ref
0
4
COMPACRIS
Analog Comparator Raw Interrupt Status
0x4
read-write
n
0x0
0x0
COMP_ACRIS_IN0
Comparator 0 Interrupt Status
0
1
COMP_ACRIS_IN1
Comparator 1 Interrupt Status
1
2
COMP_ACRIS_IN2
Comparator 2 Interrupt Status
2
3
COMPACSTAT0
Analog Comparator Status 0
0x20
read-write
n
0x0
0x0
COMP_ACSTAT0_OVAL
Comparator Output Value
1
2
COMPACSTAT1
Analog Comparator Status 1
0x40
read-write
n
0x0
0x0
COMP_ACSTAT1_OVAL
Comparator Output Value
1
2
COMPACSTAT2
Analog Comparator Status 2
0x60
read-write
n
0x0
0x0
COMP_ACSTAT2_OVAL
Comparator Output Value
1
2
FLASH_CTRL
Register map for FLASH_CTRL peripheral
FLASH_CTRL
0x0
0x0
0x1000
registers
n
0x1000
0x1000
registers
n
FCIM
Flash Controller Interrupt Mask
0x10
-1
read-write
n
0x0
0x0
FLASH_FCIM_AMASK
Access Interrupt Mask
0
1
FLASH_FCIM_PMASK
Programming Interrupt Mask
1
2
FCMISC
Flash Controller Masked Interrupt Status and Clear
0x14
-1
read-write
n
0x0
0x0
FLASH_FCMISC_AMISC
Access Masked Interrupt Status and Clear
0
1
FLASH_FCMISC_PMISC
Programming Masked Interrupt Status and Clear
1
2
FCRIS
Flash Controller Raw Interrupt Status
0xC
-1
read-write
n
0x0
0x0
FLASH_FCRIS_ARIS
Access Raw Interrupt Status
0
1
FLASH_FCRIS_PRIS
Programming Raw Interrupt Status
1
2
FLASH_CTRLFCIM
Flash Controller Interrupt Mask
0x10
read-write
n
0x0
0x0
FLASH_FCIM_AMASK
Access Interrupt Mask
0
1
FLASH_FCIM_PMASK
Programming Interrupt Mask
1
2
FLASH_CTRLFCMISC
Flash Controller Masked Interrupt Status and Clear
0x14
read-write
n
0x0
0x0
FLASH_FCMISC_AMISC
Access Masked Interrupt Status and Clear
0
1
FLASH_FCMISC_PMISC
Programming Masked Interrupt Status and Clear
1
2
FLASH_CTRLFCRIS
Flash Controller Raw Interrupt Status
0xC
read-write
n
0x0
0x0
FLASH_FCRIS_ARIS
Access Raw Interrupt Status
0
1
FLASH_FCRIS_PRIS
Programming Raw Interrupt Status
1
2
FLASH_CTRLFMA
Flash Memory Address
0x0
read-write
n
0x0
0x0
FLASH_FMA_OFFSET
Address Offset
0
17
FLASH_CTRLFMC
Flash Memory Control
0x8
read-write
n
0x0
0x0
FLASH_FMC_COMT
Commit Register Value
3
4
FLASH_FMC_ERASE
Erase a Page of Flash Memory
1
2
FLASH_FMC_MERASE
Mass Erase Flash Memory
2
3
FLASH_FMC_WRITE
Write a Word into Flash Memory
0
1
FLASH_FMC_WRKEY
FLASH write key
17
32
FLASH_CTRLFMD
Flash Memory Data
0x4
read-write
n
0x0
0x0
FLASH_FMD_DATA
Data Value
0
32
FLASH_CTRLFMPPE0
Flash Memory Protection Program Enable 0
0x1400
read-write
n
0x0
0x0
FLASH_CTRLFMPPE1
Flash Memory Protection Program Enable 1
0x1404
read-write
n
0x0
0x0
FLASH_CTRLFMPPE2
Flash Memory Protection Program Enable 2
0x1408
read-write
n
0x0
0x0
FLASH_CTRLFMPPE3
Flash Memory Protection Program Enable 3
0x140C
read-write
n
0x0
0x0
FLASH_CTRLFMPRE0
Flash Memory Protection Read Enable 0
0x1200
read-write
n
0x0
0x0
FLASH_CTRLFMPRE1
Flash Memory Protection Read Enable 1
0x1204
read-write
n
0x0
0x0
FLASH_CTRLFMPRE2
Flash Memory Protection Read Enable 2
0x1208
read-write
n
0x0
0x0
FLASH_CTRLFMPRE3
Flash Memory Protection Read Enable 3
0x120C
read-write
n
0x0
0x0
FLASH_CTRLRMCTL
ROM Control
0x10F0
read-write
n
0x0
0x0
FLASH_RMCTL_BA
Boot Alias
0
1
FLASH_CTRLUSECRL
USec Reload
0x1140
read-write
n
0x0
0x0
FLASH_USECRL
Microsecond Reload Value
0
8
FLASH_CTRLUSERDBG
User Debug
FLASH_ALT
0x11D0
read-write
n
0x0
0x0
FLASH_USERDBG_DATA
User Data
2
31
FLASH_USERDBG_DBG0
Debug Control 0
0
1
FLASH_USERDBG_DBG1
Debug Control 1
1
2
FLASH_USERDBG_NW
User Debug Not Written
31
32
FLASH_CTRLUSERREG0
User Register 0
0x11E0
read-write
n
0x0
0x0
FLASH_USERREG0_DATA
User Data
0
31
FLASH_USERREG0_NW
Not Written
31
32
FLASH_CTRLUSERREG1
User Register 1
0x11E4
read-write
n
0x0
0x0
FLASH_USERREG1_DATA
User Data
0
31
FLASH_USERREG1_NW
Not Written
31
32
FLASH_CTRLUSERREG2
User Register 2
0x11E8
read-write
n
0x0
0x0
FLASH_USERREG2_DATA
User Data
0
31
FLASH_USERREG2_NW
Not Written
31
32
FLASH_CTRLUSERREG3
User Register 3
0x11EC
read-write
n
0x0
0x0
FLASH_USERREG3_DATA
User Data
0
31
FLASH_USERREG3_NW
Not Written
31
32
FMA
Flash Memory Address
0x0
-1
read-write
n
0x0
0x0
FLASH_FMA_OFFSET
Address Offset
0
17
FMC
Flash Memory Control
0x8
-1
read-write
n
0x0
0x0
FLASH_FMC_COMT
Commit Register Value
3
4
FLASH_FMC_ERASE
Erase a Page of Flash Memory
1
2
FLASH_FMC_MERASE
Mass Erase Flash Memory
2
3
FLASH_FMC_WRITE
Write a Word into Flash Memory
0
1
FLASH_FMC_WRKEY
FLASH write key
17
32
FMD
Flash Memory Data
0x4
-1
read-write
n
0x0
0x0
FLASH_FMD_DATA
Data Value
0
32
FMPPE0
Flash Memory Protection Program Enable 0
0x1400
-1
read-write
n
0x0
0x0
FMPPE1
Flash Memory Protection Program Enable 1
0x1404
-1
read-write
n
0x0
0x0
FMPPE2
Flash Memory Protection Program Enable 2
0x1408
-1
read-write
n
0x0
0x0
FMPPE3
Flash Memory Protection Program Enable 3
0x140C
-1
read-write
n
0x0
0x0
FMPRE0
Flash Memory Protection Read Enable 0
0x1200
-1
read-write
n
0x0
0x0
FMPRE1
Flash Memory Protection Read Enable 1
0x1204
-1
read-write
n
0x0
0x0
FMPRE2
Flash Memory Protection Read Enable 2
0x1208
-1
read-write
n
0x0
0x0
FMPRE3
Flash Memory Protection Read Enable 3
0x120C
-1
read-write
n
0x0
0x0
RMCTL
ROM Control
0x10F0
-1
read-write
n
0x0
0x0
FLASH_RMCTL_BA
Boot Alias
0
1
USECRL
USec Reload
0x1140
-1
read-write
n
0x0
0x0
FLASH_USECRL
Microsecond Reload Value
0
8
USERDBG
User Debug
0x11D0
-1
read-write
n
0x0
0x0
FLASH_USERDBG_DATA
User Data
2
31
FLASH_USERDBG_DBG0
Debug Control 0
0
1
FLASH_USERDBG_DBG1
Debug Control 1
1
2
FLASH_USERDBG_NW
User Debug Not Written
31
32
USERREG0
User Register 0
0x11E0
-1
read-write
n
0x0
0x0
FLASH_USERREG0_DATA
User Data
0
31
FLASH_USERREG0_NW
Not Written
31
32
USERREG1
User Register 1
0x11E4
-1
read-write
n
0x0
0x0
FLASH_USERREG1_DATA
User Data
0
31
FLASH_USERREG1_NW
Not Written
31
32
USERREG2
User Register 2
0x11E8
-1
read-write
n
0x0
0x0
FLASH_USERREG2_DATA
User Data
0
31
FLASH_USERREG2_NW
Not Written
31
32
USERREG3
User Register 3
0x11EC
-1
read-write
n
0x0
0x0
FLASH_USERREG3_DATA
User Data
0
31
FLASH_USERREG3_NW
Not Written
31
32
GPIO_PORTA
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTA_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTB_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTC
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTC_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTD
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTD_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTE
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
GPIO_PORTE_AHB
Register map for GPIO_PORTA peripheral
GPIO_PORT
0x0
0x0
0x1000
registers
n
AFSEL
GPIO Alternate Function Select
0x420
-1
read-write
n
0x0
0x0
AMSEL
GPIO Analog Mode Select
0x528
-1
read-write
n
0x0
0x0
CR
GPIO Commit
0x524
-1
read-only
n
0x0
0x0
DATA
GPIO Data
0x3FC
-1
read-write
n
0x0
0x0
DEN
GPIO Digital Enable
0x51C
-1
read-write
n
0x0
0x0
DIR
GPIO Direction
0x400
-1
read-write
n
0x0
0x0
DR2R
GPIO 2-mA Drive Select
0x500
-1
read-write
n
0x0
0x0
DR4R
GPIO 4-mA Drive Select
0x504
-1
read-write
n
0x0
0x0
DR8R
GPIO 8-mA Drive Select
0x508
-1
read-write
n
0x0
0x0
GPIO_PORTAAFSEL
GPIO Alternate Function Select
0x420
read-write
n
0x0
0x0
GPIO_PORTAAMSEL
GPIO Analog Mode Select
0x528
read-write
n
0x0
0x0
GPIO_PORTACR
GPIO Commit
0x524
read-only
n
0x0
0x0
GPIO_PORTADATA
GPIO Data
0x3FC
read-write
n
0x0
0x0
GPIO_PORTADEN
GPIO Digital Enable
0x51C
read-write
n
0x0
0x0
GPIO_PORTADIR
GPIO Direction
0x400
read-write
n
0x0
0x0
GPIO_PORTADR2R
GPIO 2-mA Drive Select
0x500
read-write
n
0x0
0x0
GPIO_PORTADR4R
GPIO 4-mA Drive Select
0x504
read-write
n
0x0
0x0
GPIO_PORTADR8R
GPIO 8-mA Drive Select
0x508
read-write
n
0x0
0x0
GPIO_PORTAIBE
GPIO Interrupt Both Edges
0x408
read-write
n
0x0
0x0
GPIO_PORTAICR
GPIO Interrupt Clear
0x41C
write-only
n
0x0
0x0
GPIO_PORTAIEV
GPIO Interrupt Event
0x40C
read-write
n
0x0
0x0
GPIO_PORTAIM
GPIO Interrupt Mask
0x410
read-write
n
0x0
0x0
GPIO_PORTAIS
GPIO Interrupt Sense
0x404
read-write
n
0x0
0x0
GPIO_PORTALOCK
GPIO Lock
0x520
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
GPIO_PORTAMIS
GPIO Masked Interrupt Status
0x418
read-write
n
0x0
0x0
GPIO_PORTAODR
GPIO Open Drain Select
0x50C
read-write
n
0x0
0x0
GPIO_PORTAPDR
GPIO Pull-Down Select
0x514
read-write
n
0x0
0x0
GPIO_PORTAPUR
GPIO Pull-Up Select
0x510
read-write
n
0x0
0x0
GPIO_PORTARIS
GPIO Raw Interrupt Status
0x414
read-write
n
0x0
0x0
GPIO_PORTASLR
GPIO Slew Rate Control Select
0x518
read-write
n
0x0
0x0
IBE
GPIO Interrupt Both Edges
0x408
-1
read-write
n
0x0
0x0
ICR
GPIO Interrupt Clear
0x41C
-1
write-only
n
0x0
0x0
IEV
GPIO Interrupt Event
0x40C
-1
read-write
n
0x0
0x0
IM
GPIO Interrupt Mask
0x410
-1
read-write
n
0x0
0x0
IS
GPIO Interrupt Sense
0x404
-1
read-write
n
0x0
0x0
LOCK
GPIO Lock
0x520
-1
read-write
n
0x0
0x0
GPIO_LOCK
GPIO Lock
0
32
GPIO_LOCK_UNLOCKED
The GPIOCR register is unlocked and may be modified
0x0
GPIO_LOCK_LOCKED
The GPIOCR register is locked and may not be modified
0x1
GPIO_LOCK_KEY
Unlocks the GPIO_CR register
0x4c4f434b
MIS
GPIO Masked Interrupt Status
0x418
-1
read-write
n
0x0
0x0
ODR
GPIO Open Drain Select
0x50C
-1
read-write
n
0x0
0x0
PDR
GPIO Pull-Down Select
0x514
-1
read-write
n
0x0
0x0
PUR
GPIO Pull-Up Select
0x510
-1
read-write
n
0x0
0x0
RIS
GPIO Raw Interrupt Status
0x414
-1
read-write
n
0x0
0x0
SLR
GPIO Slew Rate Control Select
0x518
-1
read-write
n
0x0
0x0
I2C0
Register map for I2C0 peripheral
I2C
0x0
0x0
0x1000
registers
n
I2C0MCR
I2C Master Configuration
0x20
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
I2C0MCS
I2C Master Control/Status
0x4
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C0MDR
I2C Master Data
0x8
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
I2C0MICR
I2C Master Interrupt Clear
0x1C
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
I2C0MIMR
I2C Master Interrupt Mask
0x10
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
I2C0MMIS
I2C Master Masked Interrupt Status
0x18
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
I2C0MRIS
I2C Master Raw Interrupt Status
0x14
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
I2C0MSA
I2C Master Slave Address
0x0
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
I2C0MTPR
I2C Master Timer Period
0xC
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
I2C0SCSR
I2C Slave Control/Status
0x804
read-write
n
0x0
0x0
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
I2C0SDR
I2C Slave Data
0x808
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
I2C0SICR
I2C Slave Interrupt Clear
0x818
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
I2C0SIMR
I2C Slave Interrupt Mask
0x80C
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
I2C0SMIS
I2C Slave Masked Interrupt Status
0x814
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
I2C0SOAR
I2C Slave Own Address
0x800
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
I2C0SRIS
I2C Slave Raw Interrupt Status
0x810
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
MCR
I2C Master Configuration
0x20
-1
read-write
n
0x0
0x0
I2C_MCR_LPBK
I2C Loopback
0
1
I2C_MCR_MFE
I2C Master Function Enable
4
5
I2C_MCR_SFE
I2C Slave Function Enable
5
6
MCS
I2C Master Control/Status
0x4
-1
read-write
n
0x0
0x0
I2C_MCS_ACK
Data Acknowledge Enable
3
4
I2C_MCS_ADRACK
Acknowledge Address
2
3
I2C_MCS_ARBLST
Arbitration Lost
4
5
I2C_MCS_BUSBSY
Bus Busy
6
7
I2C_MCS_BUSY
I2C Busy
0
1
I2C_MCS_DATACK
Acknowledge Data
3
4
I2C_MCS_ERROR
Error
1
2
I2C_MCS_IDLE
I2C Idle
5
6
I2C_MCS_RUN
I2C Master Enable
0
1
I2C_MCS_START
Generate START
1
2
I2C_MCS_STOP
Generate STOP
2
3
MDR
I2C Master Data
0x8
-1
read-write
n
0x0
0x0
I2C_MDR_DATA
Data Transferred
0
8
MICR
I2C Master Interrupt Clear
0x1C
-1
write-only
n
0x0
0x0
I2C_MICR_IC
Interrupt Clear
0
1
write-only
MIMR
I2C Master Interrupt Mask
0x10
-1
read-write
n
0x0
0x0
I2C_MIMR_IM
Interrupt Mask
0
1
MMIS
I2C Master Masked Interrupt Status
0x18
-1
read-write
n
0x0
0x0
I2C_MMIS_MIS
Masked Interrupt Status
0
1
MRIS
I2C Master Raw Interrupt Status
0x14
-1
read-write
n
0x0
0x0
I2C_MRIS_RIS
Raw Interrupt Status
0
1
MSA
I2C Master Slave Address
0x0
-1
read-write
n
0x0
0x0
I2C_MSA_RS
Receive not send
0
1
I2C_MSA_SA
I2C Slave Address
1
8
MTPR
I2C Master Timer Period
0xC
-1
read-write
n
0x0
0x0
I2C_MTPR_TPR
SCL Clock Period
0
7
SCSR
I2C Slave Control/Status
0x804
-1
read-write
n
0x0
0x0
I2C_SCSR_DA
Device Active
0
1
I2C_SCSR_FBR
First Byte Received
2
3
I2C_SCSR_RREQ
Receive Request
0
1
I2C_SCSR_TREQ
Transmit Request
1
2
SDR
I2C Slave Data
0x808
-1
read-write
n
0x0
0x0
I2C_SDR_DATA
Data for Transfer
0
8
SICR
I2C Slave Interrupt Clear
0x818
-1
write-only
n
0x0
0x0
I2C_SICR_DATAIC
Data Interrupt Clear
0
1
write-only
SIMR
I2C Slave Interrupt Mask
0x80C
-1
read-write
n
0x0
0x0
I2C_SIMR_DATAIM
Data Interrupt Mask
0
1
SMIS
I2C Slave Masked Interrupt Status
0x814
-1
read-write
n
0x0
0x0
I2C_SMIS_DATAMIS
Data Masked Interrupt Status
0
1
SOAR
I2C Slave Own Address
0x800
-1
read-write
n
0x0
0x0
I2C_SOAR_OAR
I2C Slave Own Address
0
7
SRIS
I2C Slave Raw Interrupt Status
0x810
-1
read-write
n
0x0
0x0
I2C_SRIS_DATARIS
Data Raw Interrupt Status
0
1
NVIC
Register map for NVIC peripheral
NVIC
0x0
0x0
0x1000
registers
n
ACTIVE0
Interrupt 0-31 Active Bit
0x300
-1
read-write
n
0x0
0x0
NVIC_ACTIVE0_INT
Interrupt Active
0
32
NVIC_ACTIVE0_INT0
Interrupt 0 active
0x1
NVIC_ACTIVE0_INT4
Interrupt 4 active
0x10
NVIC_ACTIVE0_INT8
Interrupt 8 active
0x100
NVIC_ACTIVE0_INT12
Interrupt 12 active
0x1000
NVIC_ACTIVE0_INT16
Interrupt 16 active
0x10000
NVIC_ACTIVE0_INT20
Interrupt 20 active
0x100000
NVIC_ACTIVE0_INT24
Interrupt 24 active
0x1000000
NVIC_ACTIVE0_INT28
Interrupt 28 active
0x10000000
NVIC_ACTIVE0_INT1
Interrupt 1 active
0x2
NVIC_ACTIVE0_INT5
Interrupt 5 active
0x20
NVIC_ACTIVE0_INT9
Interrupt 9 active
0x200
NVIC_ACTIVE0_INT13
Interrupt 13 active
0x2000
NVIC_ACTIVE0_INT17
Interrupt 17 active
0x20000
NVIC_ACTIVE0_INT21
Interrupt 21 active
0x200000
NVIC_ACTIVE0_INT25
Interrupt 25 active
0x2000000
NVIC_ACTIVE0_INT29
Interrupt 29 active
0x20000000
NVIC_ACTIVE0_INT2
Interrupt 2 active
0x4
NVIC_ACTIVE0_INT6
Interrupt 6 active
0x40
NVIC_ACTIVE0_INT10
Interrupt 10 active
0x400
NVIC_ACTIVE0_INT14
Interrupt 14 active
0x4000
NVIC_ACTIVE0_INT18
Interrupt 18 active
0x40000
NVIC_ACTIVE0_INT22
Interrupt 22 active
0x400000
NVIC_ACTIVE0_INT26
Interrupt 26 active
0x4000000
NVIC_ACTIVE0_INT30
Interrupt 30 active
0x40000000
NVIC_ACTIVE0_INT3
Interrupt 3 active
0x8
NVIC_ACTIVE0_INT7
Interrupt 7 active
0x80
NVIC_ACTIVE0_INT11
Interrupt 11 active
0x800
NVIC_ACTIVE0_INT15
Interrupt 15 active
0x8000
NVIC_ACTIVE0_INT19
Interrupt 19 active
0x80000
NVIC_ACTIVE0_INT23
Interrupt 23 active
0x800000
NVIC_ACTIVE0_INT27
Interrupt 27 active
0x8000000
NVIC_ACTIVE0_INT31
Interrupt 31 active
0x80000000
ACTIVE1
Interrupt 32-54 Active Bit
0x304
-1
read-write
n
0x0
0x0
NVIC_ACTIVE1_INT
Interrupt Active
0
16
NVIC_ACTIVE1_INT32
Interrupt 32 active
0x1
NVIC_ACTIVE1_INT36
Interrupt 36 active
0x10
NVIC_ACTIVE1_INT40
Interrupt 40 active
0x100
NVIC_ACTIVE1_INT44
Interrupt 44 active
0x1000
NVIC_ACTIVE1_INT33
Interrupt 33 active
0x2
NVIC_ACTIVE1_INT37
Interrupt 37 active
0x20
NVIC_ACTIVE1_INT41
Interrupt 41 active
0x200
NVIC_ACTIVE1_INT45
Interrupt 45 active
0x2000
NVIC_ACTIVE1_INT34
Interrupt 34 active
0x4
NVIC_ACTIVE1_INT38
Interrupt 38 active
0x40
NVIC_ACTIVE1_INT42
Interrupt 42 active
0x400
NVIC_ACTIVE1_INT46
Interrupt 46 active
0x4000
NVIC_ACTIVE1_INT35
Interrupt 35 active
0x8
NVIC_ACTIVE1_INT39
Interrupt 39 active
0x80
NVIC_ACTIVE1_INT43
Interrupt 43 active
0x800
NVIC_ACTIVE1_INT47
Interrupt 47 active
0x8000
APINT
Application Interrupt and Reset Control
0xD0C
-1
read-write
n
0x0
0x0
NVIC_APINT_ENDIANESS
Data Endianess
15
16
NVIC_APINT_PRIGROUP
Interrupt Priority Grouping
8
11
NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x0
NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x1
NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x2
NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x3
NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x4
NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x5
NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x6
NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
0x7
NVIC_APINT_SYSRESETREQ
System Reset Request
2
3
NVIC_APINT_VECTKEY
Register Key
16
32
NVIC_APINT_VECTKEY
Vector key
0x5fa
NVIC_APINT_VECT_CLR_ACT
Clear Active NMI / Fault
1
2
NVIC_APINT_VECT_RESET
System Reset
0
1
CFG_CTRL
Configuration and Control
0xD14
-1
read-write
n
0x0
0x0
NVIC_CFG_CTRL_BASE_THR
Thread State Control
0
1
NVIC_CFG_CTRL_BFHFNMIGN
Ignore Bus Fault in NMI and Fault
8
9
NVIC_CFG_CTRL_DIV0
Trap on Divide by 0
4
5
NVIC_CFG_CTRL_MAIN_PEND
Allow Main Interrupt Trigger
1
2
NVIC_CFG_CTRL_STKALIGN
Stack Alignment on Exception Entry
9
10
NVIC_CFG_CTRL_UNALIGNED
Trap on Unaligned Access
3
4
CPUID
CPU ID Base
0xD00
-1
read-write
n
0x0
0x0
NVIC_CPUID_CON
Constant
16
20
NVIC_CPUID_IMP
Implementer Code
24
32
NVIC_CPUID_IMP_ARM
ARM
0x41
NVIC_CPUID_PARTNO
Part Number
4
16
NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
0xc23
NVIC_CPUID_REV
Revision Number
0
4
NVIC_CPUID_VAR
Variant Number
20
24
DBG_CTRL
Debug Control and Status Reg
0xDF0
-1
read-write
n
0x0
0x0
NVIC_DBG_CTRL_C_DEBUGEN
Enable debug
0
1
NVIC_DBG_CTRL_C_HALT
Halt the core
1
2
NVIC_DBG_CTRL_C_MASKINT
Mask interrupts when stepping
3
4
NVIC_DBG_CTRL_C_SNAPSTALL
Breaks a stalled load/store
5
6
NVIC_DBG_CTRL_C_STEP
Step the core
2
3
NVIC_DBG_CTRL_S_HALT
Core status on halt
17
18
NVIC_DBG_CTRL_S_LOCKUP
Core is locked up
19
20
NVIC_DBG_CTRL_S_REGRDY
Register read/write available
16
17
NVIC_DBG_CTRL_S_RESET_ST
Core has reset since last read
25
26
NVIC_DBG_CTRL_S_RETIRE_ST
Core has executed insruction since last read
24
25
NVIC_DBG_CTRL_S_SLEEP
Core is sleeping
18
19
DBG_DATA
Debug Core Register Data
0xDF8
-1
read-write
n
0x0
0x0
NVIC_DBG_DATA
Data temporary cache
0
32
DBG_INT
Debug Reset Interrupt Control
0xDFC
-1
read-write
n
0x0
0x0
NVIC_DBG_INT_BUSERR
Debug trap on bus error
8
9
NVIC_DBG_INT_CHKERR
Debug trap on usage fault check
6
7
NVIC_DBG_INT_HARDERR
Debug trap on hard fault
10
11
NVIC_DBG_INT_INTERR
Debug trap on interrupt errors
9
10
NVIC_DBG_INT_MMERR
Debug trap on mem manage fault
4
5
NVIC_DBG_INT_NOCPERR
Debug trap on coprocessor error
5
6
NVIC_DBG_INT_RESET
Core reset status
3
4
NVIC_DBG_INT_RSTPENDCLR
Clear pending core reset
2
3
NVIC_DBG_INT_RSTPENDING
Core reset is pending
1
2
NVIC_DBG_INT_RSTVCATCH
Reset vector catch
0
1
NVIC_DBG_INT_STATERR
Debug trap on usage fault state
7
8
DBG_XFER
Debug Core Reg. Transfer Select
0xDF4
-1
read-write
n
0x0
0x0
NVIC_DBG_XFER_REG_SEL
Register
0
5
NVIC_DBG_XFER_REG_R0
Register R0
0x0
NVIC_DBG_XFER_REG_R1
Register R1
0x1
NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x10
NVIC_DBG_XFER_REG_MSP
Main SP
0x11
NVIC_DBG_XFER_REG_PSP
Process SP
0x12
NVIC_DBG_XFER_REG_DSP
Deep SP
0x13
NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
0x14
NVIC_DBG_XFER_REG_R2
Register R2
0x2
NVIC_DBG_XFER_REG_R3
Register R3
0x3
NVIC_DBG_XFER_REG_R4
Register R4
0x4
NVIC_DBG_XFER_REG_R5
Register R5
0x5
NVIC_DBG_XFER_REG_R6
Register R6
0x6
NVIC_DBG_XFER_REG_R7
Register R7
0x7
NVIC_DBG_XFER_REG_R8
Register R8
0x8
NVIC_DBG_XFER_REG_R9
Register R9
0x9
NVIC_DBG_XFER_REG_R10
Register R10
0xa
NVIC_DBG_XFER_REG_R11
Register R11
0xb
NVIC_DBG_XFER_REG_R12
Register R12
0xc
NVIC_DBG_XFER_REG_R13
Register R13
0xd
NVIC_DBG_XFER_REG_R14
Register R14
0xe
NVIC_DBG_XFER_REG_R15
Register R15
0xf
NVIC_DBG_XFER_REG_WNR
Write or not read
16
17
DEBUG_STAT
Debug Status Register
0xD30
-1
read-write
n
0x0
0x0
NVIC_DEBUG_STAT_BKPT
Breakpoint instruction
1
2
NVIC_DEBUG_STAT_DWTTRAP
DWT match
2
3
NVIC_DEBUG_STAT_EXTRNL
EDBGRQ asserted
4
5
NVIC_DEBUG_STAT_HALTED
Halt request
0
1
NVIC_DEBUG_STAT_VCATCH
Vector catch
3
4
DIS0
Interrupt 0-31 Clear Enable
0x180
-1
read-write
n
0x0
0x0
NVIC_DIS0_INT
Interrupt Disable
0
32
NVIC_DIS0_INT0
Interrupt 0 disable
0x1
NVIC_DIS0_INT4
Interrupt 4 disable
0x10
NVIC_DIS0_INT8
Interrupt 8 disable
0x100
NVIC_DIS0_INT12
Interrupt 12 disable
0x1000
NVIC_DIS0_INT16
Interrupt 16 disable
0x10000
NVIC_DIS0_INT20
Interrupt 20 disable
0x100000
NVIC_DIS0_INT24
Interrupt 24 disable
0x1000000
NVIC_DIS0_INT28
Interrupt 28 disable
0x10000000
NVIC_DIS0_INT1
Interrupt 1 disable
0x2
NVIC_DIS0_INT5
Interrupt 5 disable
0x20
NVIC_DIS0_INT9
Interrupt 9 disable
0x200
NVIC_DIS0_INT13
Interrupt 13 disable
0x2000
NVIC_DIS0_INT17
Interrupt 17 disable
0x20000
NVIC_DIS0_INT21
Interrupt 21 disable
0x200000
NVIC_DIS0_INT25
Interrupt 25 disable
0x2000000
NVIC_DIS0_INT29
Interrupt 29 disable
0x20000000
NVIC_DIS0_INT2
Interrupt 2 disable
0x4
NVIC_DIS0_INT6
Interrupt 6 disable
0x40
NVIC_DIS0_INT10
Interrupt 10 disable
0x400
NVIC_DIS0_INT14
Interrupt 14 disable
0x4000
NVIC_DIS0_INT18
Interrupt 18 disable
0x40000
NVIC_DIS0_INT22
Interrupt 22 disable
0x400000
NVIC_DIS0_INT26
Interrupt 26 disable
0x4000000
NVIC_DIS0_INT30
Interrupt 30 disable
0x40000000
NVIC_DIS0_INT3
Interrupt 3 disable
0x8
NVIC_DIS0_INT7
Interrupt 7 disable
0x80
NVIC_DIS0_INT11
Interrupt 11 disable
0x800
NVIC_DIS0_INT15
Interrupt 15 disable
0x8000
NVIC_DIS0_INT19
Interrupt 19 disable
0x80000
NVIC_DIS0_INT23
Interrupt 23 disable
0x800000
NVIC_DIS0_INT27
Interrupt 27 disable
0x8000000
NVIC_DIS0_INT31
Interrupt 31 disable
0x80000000
DIS1
Interrupt 32-54 Clear Enable
0x184
-1
read-write
n
0x0
0x0
NVIC_DIS1_INT
Interrupt Disable
0
16
NVIC_DIS1_INT32
Interrupt 32 disable
0x1
NVIC_DIS1_INT36
Interrupt 36 disable
0x10
NVIC_DIS1_INT40
Interrupt 40 disable
0x100
NVIC_DIS1_INT44
Interrupt 44 disable
0x1000
NVIC_DIS1_INT33
Interrupt 33 disable
0x2
NVIC_DIS1_INT37
Interrupt 37 disable
0x20
NVIC_DIS1_INT41
Interrupt 41 disable
0x200
NVIC_DIS1_INT45
Interrupt 45 disable
0x2000
NVIC_DIS1_INT34
Interrupt 34 disable
0x4
NVIC_DIS1_INT38
Interrupt 38 disable
0x40
NVIC_DIS1_INT42
Interrupt 42 disable
0x400
NVIC_DIS1_INT46
Interrupt 46 disable
0x4000
NVIC_DIS1_INT35
Interrupt 35 disable
0x8
NVIC_DIS1_INT39
Interrupt 39 disable
0x80
NVIC_DIS1_INT43
Interrupt 43 disable
0x800
NVIC_DIS1_INT47
Interrupt 47 disable
0x8000
EN0
Interrupt 0-31 Set Enable
0x100
-1
read-write
n
0x0
0x0
NVIC_EN0_INT
Interrupt Enable
0
32
NVIC_EN0_INT0
Interrupt 0 enable
0x1
NVIC_EN0_INT4
Interrupt 4 enable
0x10
NVIC_EN0_INT8
Interrupt 8 enable
0x100
NVIC_EN0_INT12
Interrupt 12 enable
0x1000
NVIC_EN0_INT16
Interrupt 16 enable
0x10000
NVIC_EN0_INT20
Interrupt 20 enable
0x100000
NVIC_EN0_INT24
Interrupt 24 enable
0x1000000
NVIC_EN0_INT28
Interrupt 28 enable
0x10000000
NVIC_EN0_INT1
Interrupt 1 enable
0x2
NVIC_EN0_INT5
Interrupt 5 enable
0x20
NVIC_EN0_INT9
Interrupt 9 enable
0x200
NVIC_EN0_INT13
Interrupt 13 enable
0x2000
NVIC_EN0_INT17
Interrupt 17 enable
0x20000
NVIC_EN0_INT21
Interrupt 21 enable
0x200000
NVIC_EN0_INT25
Interrupt 25 enable
0x2000000
NVIC_EN0_INT29
Interrupt 29 enable
0x20000000
NVIC_EN0_INT2
Interrupt 2 enable
0x4
NVIC_EN0_INT6
Interrupt 6 enable
0x40
NVIC_EN0_INT10
Interrupt 10 enable
0x400
NVIC_EN0_INT14
Interrupt 14 enable
0x4000
NVIC_EN0_INT18
Interrupt 18 enable
0x40000
NVIC_EN0_INT22
Interrupt 22 enable
0x400000
NVIC_EN0_INT26
Interrupt 26 enable
0x4000000
NVIC_EN0_INT30
Interrupt 30 enable
0x40000000
NVIC_EN0_INT3
Interrupt 3 enable
0x8
NVIC_EN0_INT7
Interrupt 7 enable
0x80
NVIC_EN0_INT11
Interrupt 11 enable
0x800
NVIC_EN0_INT15
Interrupt 15 enable
0x8000
NVIC_EN0_INT19
Interrupt 19 enable
0x80000
NVIC_EN0_INT23
Interrupt 23 enable
0x800000
NVIC_EN0_INT27
Interrupt 27 enable
0x8000000
NVIC_EN0_INT31
Interrupt 31 enable
0x80000000
EN1
Interrupt 32-54 Set Enable
0x104
-1
read-write
n
0x0
0x0
NVIC_EN1_INT
Interrupt Enable
0
16
NVIC_EN1_INT32
Interrupt 32 enable
0x1
NVIC_EN1_INT36
Interrupt 36 enable
0x10
NVIC_EN1_INT40
Interrupt 40 enable
0x100
NVIC_EN1_INT44
Interrupt 44 enable
0x1000
NVIC_EN1_INT33
Interrupt 33 enable
0x2
NVIC_EN1_INT37
Interrupt 37 enable
0x20
NVIC_EN1_INT41
Interrupt 41 enable
0x200
NVIC_EN1_INT45
Interrupt 45 enable
0x2000
NVIC_EN1_INT34
Interrupt 34 enable
0x4
NVIC_EN1_INT38
Interrupt 38 enable
0x40
NVIC_EN1_INT42
Interrupt 42 enable
0x400
NVIC_EN1_INT46
Interrupt 46 enable
0x4000
NVIC_EN1_INT35
Interrupt 35 enable
0x8
NVIC_EN1_INT39
Interrupt 39 enable
0x80
NVIC_EN1_INT43
Interrupt 43 enable
0x800
NVIC_EN1_INT47
Interrupt 47 enable
0x8000
FAULT_ADDR
Bus Fault Address
0xD38
-1
read-write
n
0x0
0x0
NVIC_FAULT_ADDR
Fault Address
0
32
FAULT_STAT
Configurable Fault Status
0xD28
-1
read-write
n
0x0
0x0
NVIC_FAULT_STAT_BFARV
Bus Fault Address Register Valid
15
16
NVIC_FAULT_STAT_BSTKE
Stack Bus Fault
12
13
NVIC_FAULT_STAT_BUSTKE
Unstack Bus Fault
11
12
NVIC_FAULT_STAT_DERR
Data Access Violation
1
2
NVIC_FAULT_STAT_DIV0
Divide-by-Zero Usage Fault
25
26
NVIC_FAULT_STAT_IBUS
Instruction Bus Error
8
9
NVIC_FAULT_STAT_IERR
Instruction Access Violation
0
1
NVIC_FAULT_STAT_IMPRE
Imprecise Data Bus Error
10
11
NVIC_FAULT_STAT_INVPC
Invalid PC Load Usage Fault
18
19
NVIC_FAULT_STAT_INVSTAT
Invalid State Usage Fault
17
18
NVIC_FAULT_STAT_MMARV
Memory Management Fault Address Register Valid
7
8
NVIC_FAULT_STAT_MSTKE
Stack Access Violation
4
5
NVIC_FAULT_STAT_MUSTKE
Unstack Access Violation
3
4
NVIC_FAULT_STAT_NOCP
No Coprocessor Usage Fault
19
20
NVIC_FAULT_STAT_PRECISE
Precise Data Bus Error
9
10
NVIC_FAULT_STAT_UNALIGN
Unaligned Access Usage Fault
24
25
NVIC_FAULT_STAT_UNDEF
Undefined Instruction Usage Fault
16
17
HFAULT_STAT
Hard Fault Status
0xD2C
-1
read-write
n
0x0
0x0
NVIC_HFAULT_STAT_DBG
Debug Event
31
32
NVIC_HFAULT_STAT_FORCED
Forced Hard Fault
30
31
NVIC_HFAULT_STAT_VECT
Vector Table Read Fault
1
2
INT_CTRL
Interrupt Control and State
0xD04
-1
read-write
n
0x0
0x0
NVIC_INT_CTRL_ISR_PEND
Interrupt Pending
22
23
NVIC_INT_CTRL_ISR_PRE
Debug Interrupt Handling
23
24
NVIC_INT_CTRL_NMI_SET
NMI Set Pending
31
32
NVIC_INT_CTRL_PENDSTCLR
SysTick Clear Pending
25
26
NVIC_INT_CTRL_PENDSTSET
SysTick Set Pending
26
27
NVIC_INT_CTRL_PEND_SV
PendSV Set Pending
28
29
NVIC_INT_CTRL_RET_BASE
Return to Base
11
12
NVIC_INT_CTRL_UNPEND_SV
PendSV Clear Pending
27
28
NVIC_INT_CTRL_VEC_ACT
Interrupt Pending Vector Number
0
7
NVIC_INT_CTRL_VEC_PEN
Interrupt Pending Vector Number
12
19
NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x2
NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x3
NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x4
NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x5
NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0x6
NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xb
NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xe
NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
0xf
INT_TYPE
Interrupt Controller Type Reg
0x4
-1
read-write
n
0x0
0x0
NVIC_INT_TYPE_LINES
Number of interrupt lines (x32)
0
5
MM_ADDR
Memory Management Fault Address
0xD34
-1
read-write
n
0x0
0x0
NVIC_MM_ADDR
Fault Address
0
32
MPU_ATTR
MPU Region Attribute and Size
0xDA0
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR_AP
Access Privilege
24
27
NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x0
NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x1
NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x2
NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x3
NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x5
NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
0x6
NVIC_MPU_ATTR_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x10
NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x11
NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x12
NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x13
NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x14
NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x15
NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x16
NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x17
NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x18
NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x19
NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1a
NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1b
NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1c
NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1d
NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1e
NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
0x1f
NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x4
NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x5
NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x6
NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x7
NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x8
NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0x9
NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xa
NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xb
NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xc
NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xd
NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xe
NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0xf
NVIC_MPU_ATTR_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x1
NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x10
NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x2
NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x20
NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x4
NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x40
NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x8
NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
0x80
NVIC_MPU_ATTR_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR_XN
Instruction Access Disable
28
29
MPU_ATTR1
MPU Region Attribute and Size Alias 1
0xDA8
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR1_AP
Access Privilege
24
27
NVIC_MPU_ATTR1_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR1_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR1_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR1_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR1_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR1_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR1_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR1_XN
Instruction Access Disable
28
29
MPU_ATTR2
MPU Region Attribute and Size Alias 2
0xDB0
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR2_AP
Access Privilege
24
27
NVIC_MPU_ATTR2_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR2_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR2_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR2_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR2_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR2_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR2_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR2_XN
Instruction Access Disable
28
29
MPU_ATTR3
MPU Region Attribute and Size Alias 3
0xDB8
-1
read-write
n
0x0
0x0
NVIC_MPU_ATTR3_AP
Access Privilege
24
27
NVIC_MPU_ATTR3_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR3_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR3_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR3_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR3_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR3_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR3_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR3_XN
Instruction Access Disable
28
29
MPU_BASE
MPU Region Base Address
0xD9C
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE_REGION
Region Number
0
3
NVIC_MPU_BASE_VALID
Region Number Valid
4
5
MPU_BASE1
MPU Region Base Address Alias 1
0xDA4
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE1_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE1_REGION
Region Number
0
3
NVIC_MPU_BASE1_VALID
Region Number Valid
4
5
MPU_BASE2
MPU Region Base Address Alias 2
0xDAC
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE2_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE2_REGION
Region Number
0
3
NVIC_MPU_BASE2_VALID
Region Number Valid
4
5
MPU_BASE3
MPU Region Base Address Alias 3
0xDB4
-1
read-write
n
0x0
0x0
NVIC_MPU_BASE3_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE3_REGION
Region Number
0
3
NVIC_MPU_BASE3_VALID
Region Number Valid
4
5
MPU_CTRL
MPU Control
0xD94
-1
read-write
n
0x0
0x0
NVIC_MPU_CTRL_ENABLE
MPU Enable
0
1
NVIC_MPU_CTRL_HFNMIENA
MPU Enabled During Faults
1
2
NVIC_MPU_CTRL_PRIVDEFEN
MPU Default Region
2
3
MPU_NUMBER
MPU Region Number
0xD98
-1
read-write
n
0x0
0x0
NVIC_MPU_NUMBER
MPU Region to Access
0
3
MPU_TYPE
MPU Type
0xD90
-1
read-write
n
0x0
0x0
NVIC_MPU_TYPE_DREGION
Number of D Regions
8
16
NVIC_MPU_TYPE_IREGION
Number of I Regions
16
24
NVIC_MPU_TYPE_SEPARATE
Separate or Unified MPU
0
1
NVICACTIVE0
Interrupt 0-31 Active Bit
0x300
read-write
n
0x0
0x0
NVIC_ACTIVE0_INT
Interrupt Active
0
32
NVIC_ACTIVE0_INT0
Interrupt 0 active
0x1
NVIC_ACTIVE0_INT4
Interrupt 4 active
0x10
NVIC_ACTIVE0_INT8
Interrupt 8 active
0x100
NVIC_ACTIVE0_INT12
Interrupt 12 active
0x1000
NVIC_ACTIVE0_INT16
Interrupt 16 active
0x10000
NVIC_ACTIVE0_INT20
Interrupt 20 active
0x100000
NVIC_ACTIVE0_INT24
Interrupt 24 active
0x1000000
NVIC_ACTIVE0_INT28
Interrupt 28 active
0x10000000
NVIC_ACTIVE0_INT1
Interrupt 1 active
0x2
NVIC_ACTIVE0_INT5
Interrupt 5 active
0x20
NVIC_ACTIVE0_INT9
Interrupt 9 active
0x200
NVIC_ACTIVE0_INT13
Interrupt 13 active
0x2000
NVIC_ACTIVE0_INT17
Interrupt 17 active
0x20000
NVIC_ACTIVE0_INT21
Interrupt 21 active
0x200000
NVIC_ACTIVE0_INT25
Interrupt 25 active
0x2000000
NVIC_ACTIVE0_INT29
Interrupt 29 active
0x20000000
NVIC_ACTIVE0_INT2
Interrupt 2 active
0x4
NVIC_ACTIVE0_INT6
Interrupt 6 active
0x40
NVIC_ACTIVE0_INT10
Interrupt 10 active
0x400
NVIC_ACTIVE0_INT14
Interrupt 14 active
0x4000
NVIC_ACTIVE0_INT18
Interrupt 18 active
0x40000
NVIC_ACTIVE0_INT22
Interrupt 22 active
0x400000
NVIC_ACTIVE0_INT26
Interrupt 26 active
0x4000000
NVIC_ACTIVE0_INT30
Interrupt 30 active
0x40000000
NVIC_ACTIVE0_INT3
Interrupt 3 active
0x8
NVIC_ACTIVE0_INT7
Interrupt 7 active
0x80
NVIC_ACTIVE0_INT11
Interrupt 11 active
0x800
NVIC_ACTIVE0_INT15
Interrupt 15 active
0x8000
NVIC_ACTIVE0_INT19
Interrupt 19 active
0x80000
NVIC_ACTIVE0_INT23
Interrupt 23 active
0x800000
NVIC_ACTIVE0_INT27
Interrupt 27 active
0x8000000
NVIC_ACTIVE0_INT31
Interrupt 31 active
0x80000000
NVICACTIVE1
Interrupt 32-54 Active Bit
0x304
read-write
n
0x0
0x0
NVIC_ACTIVE1_INT
Interrupt Active
0
16
NVIC_ACTIVE1_INT32
Interrupt 32 active
0x1
NVIC_ACTIVE1_INT36
Interrupt 36 active
0x10
NVIC_ACTIVE1_INT40
Interrupt 40 active
0x100
NVIC_ACTIVE1_INT44
Interrupt 44 active
0x1000
NVIC_ACTIVE1_INT33
Interrupt 33 active
0x2
NVIC_ACTIVE1_INT37
Interrupt 37 active
0x20
NVIC_ACTIVE1_INT41
Interrupt 41 active
0x200
NVIC_ACTIVE1_INT45
Interrupt 45 active
0x2000
NVIC_ACTIVE1_INT34
Interrupt 34 active
0x4
NVIC_ACTIVE1_INT38
Interrupt 38 active
0x40
NVIC_ACTIVE1_INT42
Interrupt 42 active
0x400
NVIC_ACTIVE1_INT46
Interrupt 46 active
0x4000
NVIC_ACTIVE1_INT35
Interrupt 35 active
0x8
NVIC_ACTIVE1_INT39
Interrupt 39 active
0x80
NVIC_ACTIVE1_INT43
Interrupt 43 active
0x800
NVIC_ACTIVE1_INT47
Interrupt 47 active
0x8000
NVICAPINT
Application Interrupt and Reset Control
0xD0C
read-write
n
0x0
0x0
NVIC_APINT_ENDIANESS
Data Endianess
15
16
NVIC_APINT_PRIGROUP
Interrupt Priority Grouping
8
11
NVIC_APINT_PRIGROUP_7_1
Priority group 7.1 split
0x0
NVIC_APINT_PRIGROUP_6_2
Priority group 6.2 split
0x1
NVIC_APINT_PRIGROUP_5_3
Priority group 5.3 split
0x2
NVIC_APINT_PRIGROUP_4_4
Priority group 4.4 split
0x3
NVIC_APINT_PRIGROUP_3_5
Priority group 3.5 split
0x4
NVIC_APINT_PRIGROUP_2_6
Priority group 2.6 split
0x5
NVIC_APINT_PRIGROUP_1_7
Priority group 1.7 split
0x6
NVIC_APINT_PRIGROUP_0_8
Priority group 0.8 split
0x7
NVIC_APINT_SYSRESETREQ
System Reset Request
2
3
NVIC_APINT_VECTKEY
Register Key
16
32
NVIC_APINT_VECTKEY
Vector key
0x5fa
NVIC_APINT_VECT_CLR_ACT
Clear Active NMI / Fault
1
2
NVIC_APINT_VECT_RESET
System Reset
0
1
NVICCFG_CTRL
Configuration and Control
0xD14
read-write
n
0x0
0x0
NVIC_CFG_CTRL_BASE_THR
Thread State Control
0
1
NVIC_CFG_CTRL_BFHFNMIGN
Ignore Bus Fault in NMI and Fault
8
9
NVIC_CFG_CTRL_DIV0
Trap on Divide by 0
4
5
NVIC_CFG_CTRL_MAIN_PEND
Allow Main Interrupt Trigger
1
2
NVIC_CFG_CTRL_STKALIGN
Stack Alignment on Exception Entry
9
10
NVIC_CFG_CTRL_UNALIGNED
Trap on Unaligned Access
3
4
NVICCPUID
CPU ID Base
0xD00
read-write
n
0x0
0x0
NVIC_CPUID_CON
Constant
16
20
NVIC_CPUID_IMP
Implementer Code
24
32
NVIC_CPUID_IMP_ARM
ARM
0x41
NVIC_CPUID_PARTNO
Part Number
4
16
NVIC_CPUID_PARTNO_CM3
Cortex-M3 processor
0xc23
NVIC_CPUID_REV
Revision Number
0
4
NVIC_CPUID_VAR
Variant Number
20
24
NVICDBG_CTRL
Debug Control and Status Reg
0xDF0
read-write
n
0x0
0x0
NVIC_DBG_CTRL_C_DEBUGEN
Enable debug
0
1
NVIC_DBG_CTRL_C_HALT
Halt the core
1
2
NVIC_DBG_CTRL_C_MASKINT
Mask interrupts when stepping
3
4
NVIC_DBG_CTRL_C_SNAPSTALL
Breaks a stalled load/store
5
6
NVIC_DBG_CTRL_C_STEP
Step the core
2
3
NVIC_DBG_CTRL_S_HALT
Core status on halt
17
18
NVIC_DBG_CTRL_S_LOCKUP
Core is locked up
19
20
NVIC_DBG_CTRL_S_REGRDY
Register read/write available
16
17
NVIC_DBG_CTRL_S_RESET_ST
Core has reset since last read
25
26
NVIC_DBG_CTRL_S_RETIRE_ST
Core has executed insruction since last read
24
25
NVIC_DBG_CTRL_S_SLEEP
Core is sleeping
18
19
NVICDBG_DATA
Debug Core Register Data
0xDF8
read-write
n
0x0
0x0
NVIC_DBG_DATA
Data temporary cache
0
32
NVICDBG_INT
Debug Reset Interrupt Control
0xDFC
read-write
n
0x0
0x0
NVIC_DBG_INT_BUSERR
Debug trap on bus error
8
9
NVIC_DBG_INT_CHKERR
Debug trap on usage fault check
6
7
NVIC_DBG_INT_HARDERR
Debug trap on hard fault
10
11
NVIC_DBG_INT_INTERR
Debug trap on interrupt errors
9
10
NVIC_DBG_INT_MMERR
Debug trap on mem manage fault
4
5
NVIC_DBG_INT_NOCPERR
Debug trap on coprocessor error
5
6
NVIC_DBG_INT_RESET
Core reset status
3
4
NVIC_DBG_INT_RSTPENDCLR
Clear pending core reset
2
3
NVIC_DBG_INT_RSTPENDING
Core reset is pending
1
2
NVIC_DBG_INT_RSTVCATCH
Reset vector catch
0
1
NVIC_DBG_INT_STATERR
Debug trap on usage fault state
7
8
NVICDBG_XFER
Debug Core Reg. Transfer Select
0xDF4
read-write
n
0x0
0x0
NVIC_DBG_XFER_REG_SEL
Register
0
5
NVIC_DBG_XFER_REG_R0
Register R0
0x0
NVIC_DBG_XFER_REG_R1
Register R1
0x1
NVIC_DBG_XFER_REG_FLAGS
xPSR/Flags register
0x10
NVIC_DBG_XFER_REG_MSP
Main SP
0x11
NVIC_DBG_XFER_REG_PSP
Process SP
0x12
NVIC_DBG_XFER_REG_DSP
Deep SP
0x13
NVIC_DBG_XFER_REG_CFBP
Control/Fault/BasePri/PriMask
0x14
NVIC_DBG_XFER_REG_R2
Register R2
0x2
NVIC_DBG_XFER_REG_R3
Register R3
0x3
NVIC_DBG_XFER_REG_R4
Register R4
0x4
NVIC_DBG_XFER_REG_R5
Register R5
0x5
NVIC_DBG_XFER_REG_R6
Register R6
0x6
NVIC_DBG_XFER_REG_R7
Register R7
0x7
NVIC_DBG_XFER_REG_R8
Register R8
0x8
NVIC_DBG_XFER_REG_R9
Register R9
0x9
NVIC_DBG_XFER_REG_R10
Register R10
0xa
NVIC_DBG_XFER_REG_R11
Register R11
0xb
NVIC_DBG_XFER_REG_R12
Register R12
0xc
NVIC_DBG_XFER_REG_R13
Register R13
0xd
NVIC_DBG_XFER_REG_R14
Register R14
0xe
NVIC_DBG_XFER_REG_R15
Register R15
0xf
NVIC_DBG_XFER_REG_WNR
Write or not read
16
17
NVICDEBUG_STAT
Debug Status Register
0xD30
read-write
n
0x0
0x0
NVIC_DEBUG_STAT_BKPT
Breakpoint instruction
1
2
NVIC_DEBUG_STAT_DWTTRAP
DWT match
2
3
NVIC_DEBUG_STAT_EXTRNL
EDBGRQ asserted
4
5
NVIC_DEBUG_STAT_HALTED
Halt request
0
1
NVIC_DEBUG_STAT_VCATCH
Vector catch
3
4
NVICDIS0
Interrupt 0-31 Clear Enable
0x180
read-write
n
0x0
0x0
NVIC_DIS0_INT
Interrupt Disable
0
32
NVIC_DIS0_INT0
Interrupt 0 disable
0x1
NVIC_DIS0_INT4
Interrupt 4 disable
0x10
NVIC_DIS0_INT8
Interrupt 8 disable
0x100
NVIC_DIS0_INT12
Interrupt 12 disable
0x1000
NVIC_DIS0_INT16
Interrupt 16 disable
0x10000
NVIC_DIS0_INT20
Interrupt 20 disable
0x100000
NVIC_DIS0_INT24
Interrupt 24 disable
0x1000000
NVIC_DIS0_INT28
Interrupt 28 disable
0x10000000
NVIC_DIS0_INT1
Interrupt 1 disable
0x2
NVIC_DIS0_INT5
Interrupt 5 disable
0x20
NVIC_DIS0_INT9
Interrupt 9 disable
0x200
NVIC_DIS0_INT13
Interrupt 13 disable
0x2000
NVIC_DIS0_INT17
Interrupt 17 disable
0x20000
NVIC_DIS0_INT21
Interrupt 21 disable
0x200000
NVIC_DIS0_INT25
Interrupt 25 disable
0x2000000
NVIC_DIS0_INT29
Interrupt 29 disable
0x20000000
NVIC_DIS0_INT2
Interrupt 2 disable
0x4
NVIC_DIS0_INT6
Interrupt 6 disable
0x40
NVIC_DIS0_INT10
Interrupt 10 disable
0x400
NVIC_DIS0_INT14
Interrupt 14 disable
0x4000
NVIC_DIS0_INT18
Interrupt 18 disable
0x40000
NVIC_DIS0_INT22
Interrupt 22 disable
0x400000
NVIC_DIS0_INT26
Interrupt 26 disable
0x4000000
NVIC_DIS0_INT30
Interrupt 30 disable
0x40000000
NVIC_DIS0_INT3
Interrupt 3 disable
0x8
NVIC_DIS0_INT7
Interrupt 7 disable
0x80
NVIC_DIS0_INT11
Interrupt 11 disable
0x800
NVIC_DIS0_INT15
Interrupt 15 disable
0x8000
NVIC_DIS0_INT19
Interrupt 19 disable
0x80000
NVIC_DIS0_INT23
Interrupt 23 disable
0x800000
NVIC_DIS0_INT27
Interrupt 27 disable
0x8000000
NVIC_DIS0_INT31
Interrupt 31 disable
0x80000000
NVICDIS1
Interrupt 32-54 Clear Enable
0x184
read-write
n
0x0
0x0
NVIC_DIS1_INT
Interrupt Disable
0
16
NVIC_DIS1_INT32
Interrupt 32 disable
0x1
NVIC_DIS1_INT36
Interrupt 36 disable
0x10
NVIC_DIS1_INT40
Interrupt 40 disable
0x100
NVIC_DIS1_INT44
Interrupt 44 disable
0x1000
NVIC_DIS1_INT33
Interrupt 33 disable
0x2
NVIC_DIS1_INT37
Interrupt 37 disable
0x20
NVIC_DIS1_INT41
Interrupt 41 disable
0x200
NVIC_DIS1_INT45
Interrupt 45 disable
0x2000
NVIC_DIS1_INT34
Interrupt 34 disable
0x4
NVIC_DIS1_INT38
Interrupt 38 disable
0x40
NVIC_DIS1_INT42
Interrupt 42 disable
0x400
NVIC_DIS1_INT46
Interrupt 46 disable
0x4000
NVIC_DIS1_INT35
Interrupt 35 disable
0x8
NVIC_DIS1_INT39
Interrupt 39 disable
0x80
NVIC_DIS1_INT43
Interrupt 43 disable
0x800
NVIC_DIS1_INT47
Interrupt 47 disable
0x8000
NVICEN0
Interrupt 0-31 Set Enable
0x100
read-write
n
0x0
0x0
NVIC_EN0_INT
Interrupt Enable
0
32
NVIC_EN0_INT0
Interrupt 0 enable
0x1
NVIC_EN0_INT4
Interrupt 4 enable
0x10
NVIC_EN0_INT8
Interrupt 8 enable
0x100
NVIC_EN0_INT12
Interrupt 12 enable
0x1000
NVIC_EN0_INT16
Interrupt 16 enable
0x10000
NVIC_EN0_INT20
Interrupt 20 enable
0x100000
NVIC_EN0_INT24
Interrupt 24 enable
0x1000000
NVIC_EN0_INT28
Interrupt 28 enable
0x10000000
NVIC_EN0_INT1
Interrupt 1 enable
0x2
NVIC_EN0_INT5
Interrupt 5 enable
0x20
NVIC_EN0_INT9
Interrupt 9 enable
0x200
NVIC_EN0_INT13
Interrupt 13 enable
0x2000
NVIC_EN0_INT17
Interrupt 17 enable
0x20000
NVIC_EN0_INT21
Interrupt 21 enable
0x200000
NVIC_EN0_INT25
Interrupt 25 enable
0x2000000
NVIC_EN0_INT29
Interrupt 29 enable
0x20000000
NVIC_EN0_INT2
Interrupt 2 enable
0x4
NVIC_EN0_INT6
Interrupt 6 enable
0x40
NVIC_EN0_INT10
Interrupt 10 enable
0x400
NVIC_EN0_INT14
Interrupt 14 enable
0x4000
NVIC_EN0_INT18
Interrupt 18 enable
0x40000
NVIC_EN0_INT22
Interrupt 22 enable
0x400000
NVIC_EN0_INT26
Interrupt 26 enable
0x4000000
NVIC_EN0_INT30
Interrupt 30 enable
0x40000000
NVIC_EN0_INT3
Interrupt 3 enable
0x8
NVIC_EN0_INT7
Interrupt 7 enable
0x80
NVIC_EN0_INT11
Interrupt 11 enable
0x800
NVIC_EN0_INT15
Interrupt 15 enable
0x8000
NVIC_EN0_INT19
Interrupt 19 enable
0x80000
NVIC_EN0_INT23
Interrupt 23 enable
0x800000
NVIC_EN0_INT27
Interrupt 27 enable
0x8000000
NVIC_EN0_INT31
Interrupt 31 enable
0x80000000
NVICEN1
Interrupt 32-54 Set Enable
0x104
read-write
n
0x0
0x0
NVIC_EN1_INT
Interrupt Enable
0
16
NVIC_EN1_INT32
Interrupt 32 enable
0x1
NVIC_EN1_INT36
Interrupt 36 enable
0x10
NVIC_EN1_INT40
Interrupt 40 enable
0x100
NVIC_EN1_INT44
Interrupt 44 enable
0x1000
NVIC_EN1_INT33
Interrupt 33 enable
0x2
NVIC_EN1_INT37
Interrupt 37 enable
0x20
NVIC_EN1_INT41
Interrupt 41 enable
0x200
NVIC_EN1_INT45
Interrupt 45 enable
0x2000
NVIC_EN1_INT34
Interrupt 34 enable
0x4
NVIC_EN1_INT38
Interrupt 38 enable
0x40
NVIC_EN1_INT42
Interrupt 42 enable
0x400
NVIC_EN1_INT46
Interrupt 46 enable
0x4000
NVIC_EN1_INT35
Interrupt 35 enable
0x8
NVIC_EN1_INT39
Interrupt 39 enable
0x80
NVIC_EN1_INT43
Interrupt 43 enable
0x800
NVIC_EN1_INT47
Interrupt 47 enable
0x8000
NVICFAULT_ADDR
Bus Fault Address
0xD38
read-write
n
0x0
0x0
NVIC_FAULT_ADDR
Fault Address
0
32
NVICFAULT_STAT
Configurable Fault Status
0xD28
read-write
n
0x0
0x0
NVIC_FAULT_STAT_BFARV
Bus Fault Address Register Valid
15
16
NVIC_FAULT_STAT_BSTKE
Stack Bus Fault
12
13
NVIC_FAULT_STAT_BUSTKE
Unstack Bus Fault
11
12
NVIC_FAULT_STAT_DERR
Data Access Violation
1
2
NVIC_FAULT_STAT_DIV0
Divide-by-Zero Usage Fault
25
26
NVIC_FAULT_STAT_IBUS
Instruction Bus Error
8
9
NVIC_FAULT_STAT_IERR
Instruction Access Violation
0
1
NVIC_FAULT_STAT_IMPRE
Imprecise Data Bus Error
10
11
NVIC_FAULT_STAT_INVPC
Invalid PC Load Usage Fault
18
19
NVIC_FAULT_STAT_INVSTAT
Invalid State Usage Fault
17
18
NVIC_FAULT_STAT_MMARV
Memory Management Fault Address Register Valid
7
8
NVIC_FAULT_STAT_MSTKE
Stack Access Violation
4
5
NVIC_FAULT_STAT_MUSTKE
Unstack Access Violation
3
4
NVIC_FAULT_STAT_NOCP
No Coprocessor Usage Fault
19
20
NVIC_FAULT_STAT_PRECISE
Precise Data Bus Error
9
10
NVIC_FAULT_STAT_UNALIGN
Unaligned Access Usage Fault
24
25
NVIC_FAULT_STAT_UNDEF
Undefined Instruction Usage Fault
16
17
NVICHFAULT_STAT
Hard Fault Status
0xD2C
read-write
n
0x0
0x0
NVIC_HFAULT_STAT_DBG
Debug Event
31
32
NVIC_HFAULT_STAT_FORCED
Forced Hard Fault
30
31
NVIC_HFAULT_STAT_VECT
Vector Table Read Fault
1
2
NVICINT_CTRL
Interrupt Control and State
0xD04
read-write
n
0x0
0x0
NVIC_INT_CTRL_ISR_PEND
Interrupt Pending
22
23
NVIC_INT_CTRL_ISR_PRE
Debug Interrupt Handling
23
24
NVIC_INT_CTRL_NMI_SET
NMI Set Pending
31
32
NVIC_INT_CTRL_PENDSTCLR
SysTick Clear Pending
25
26
NVIC_INT_CTRL_PENDSTSET
SysTick Set Pending
26
27
NVIC_INT_CTRL_PEND_SV
PendSV Set Pending
28
29
NVIC_INT_CTRL_RET_BASE
Return to Base
11
12
NVIC_INT_CTRL_UNPEND_SV
PendSV Clear Pending
27
28
NVIC_INT_CTRL_VEC_ACT
Interrupt Pending Vector Number
0
7
NVIC_INT_CTRL_VEC_PEN
Interrupt Pending Vector Number
12
19
NVIC_INT_CTRL_VEC_PEN_NMI
NMI
0x2
NVIC_INT_CTRL_VEC_PEN_HARD
Hard fault
0x3
NVIC_INT_CTRL_VEC_PEN_MEM
Memory management fault
0x4
NVIC_INT_CTRL_VEC_PEN_BUS
Bus fault
0x5
NVIC_INT_CTRL_VEC_PEN_USG
Usage fault
0x6
NVIC_INT_CTRL_VEC_PEN_SVC
SVCall
0xb
NVIC_INT_CTRL_VEC_PEN_PNDSV
PendSV
0xe
NVIC_INT_CTRL_VEC_PEN_TICK
SysTick
0xf
NVICINT_TYPE
Interrupt Controller Type Reg
0x4
read-write
n
0x0
0x0
NVIC_INT_TYPE_LINES
Number of interrupt lines (x32)
0
5
NVICMM_ADDR
Memory Management Fault Address
0xD34
read-write
n
0x0
0x0
NVIC_MM_ADDR
Fault Address
0
32
NVICMPU_ATTR
MPU Region Attribute and Size
0xDA0
read-write
n
0x0
0x0
NVIC_MPU_ATTR_AP
Access Privilege
24
27
NVIC_MPU_ATTR_AP_NO_NO
prv: no access, usr: no access
0x0
NVIC_MPU_ATTR_AP_RW_NO
prv: rw, usr: none
0x1
NVIC_MPU_ATTR_AP_RW_RO
prv: rw, usr: read-only
0x2
NVIC_MPU_ATTR_AP_RW_RW
prv: rw, usr: rw
0x3
NVIC_MPU_ATTR_AP_RO_NO
prv: ro, usr: none
0x5
NVIC_MPU_ATTR_AP_RO_RO
prv: ro, usr: ro
0x6
NVIC_MPU_ATTR_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR_SIZE_128K
Region size 128 Kbytes
0x10
NVIC_MPU_ATTR_SIZE_256K
Region size 256 Kbytes
0x11
NVIC_MPU_ATTR_SIZE_512K
Region size 512 Kbytes
0x12
NVIC_MPU_ATTR_SIZE_1M
Region size 1 Mbytes
0x13
NVIC_MPU_ATTR_SIZE_2M
Region size 2 Mbytes
0x14
NVIC_MPU_ATTR_SIZE_4M
Region size 4 Mbytes
0x15
NVIC_MPU_ATTR_SIZE_8M
Region size 8 Mbytes
0x16
NVIC_MPU_ATTR_SIZE_16M
Region size 16 Mbytes
0x17
NVIC_MPU_ATTR_SIZE_32M
Region size 32 Mbytes
0x18
NVIC_MPU_ATTR_SIZE_64M
Region size 64 Mbytes
0x19
NVIC_MPU_ATTR_SIZE_128M
Region size 128 Mbytes
0x1a
NVIC_MPU_ATTR_SIZE_256M
Region size 256 Mbytes
0x1b
NVIC_MPU_ATTR_SIZE_512M
Region size 512 Mbytes
0x1c
NVIC_MPU_ATTR_SIZE_1G
Region size 1 Gbytes
0x1d
NVIC_MPU_ATTR_SIZE_2G
Region size 2 Gbytes
0x1e
NVIC_MPU_ATTR_SIZE_4G
Region size 4 Gbytes
0x1f
NVIC_MPU_ATTR_SIZE_32B
Region size 32 bytes
0x4
NVIC_MPU_ATTR_SIZE_64B
Region size 64 bytes
0x5
NVIC_MPU_ATTR_SIZE_128B
Region size 128 bytes
0x6
NVIC_MPU_ATTR_SIZE_256B
Region size 256 bytes
0x7
NVIC_MPU_ATTR_SIZE_512B
Region size 512 bytes
0x8
NVIC_MPU_ATTR_SIZE_1K
Region size 1 Kbytes
0x9
NVIC_MPU_ATTR_SIZE_2K
Region size 2 Kbytes
0xa
NVIC_MPU_ATTR_SIZE_4K
Region size 4 Kbytes
0xb
NVIC_MPU_ATTR_SIZE_8K
Region size 8 Kbytes
0xc
NVIC_MPU_ATTR_SIZE_16K
Region size 16 Kbytes
0xd
NVIC_MPU_ATTR_SIZE_32K
Region size 32 Kbytes
0xe
NVIC_MPU_ATTR_SIZE_64K
Region size 64 Kbytes
0xf
NVIC_MPU_ATTR_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR_SRD_0
Sub-region 0 disable
0x1
NVIC_MPU_ATTR_SRD_4
Sub-region 4 disable
0x10
NVIC_MPU_ATTR_SRD_1
Sub-region 1 disable
0x2
NVIC_MPU_ATTR_SRD_5
Sub-region 5 disable
0x20
NVIC_MPU_ATTR_SRD_2
Sub-region 2 disable
0x4
NVIC_MPU_ATTR_SRD_6
Sub-region 6 disable
0x40
NVIC_MPU_ATTR_SRD_3
Sub-region 3 disable
0x8
NVIC_MPU_ATTR_SRD_7
Sub-region 7 disable
0x80
NVIC_MPU_ATTR_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR_XN
Instruction Access Disable
28
29
NVICMPU_ATTR1
MPU Region Attribute and Size Alias 1
0xDA8
read-write
n
0x0
0x0
NVIC_MPU_ATTR1_AP
Access Privilege
24
27
NVIC_MPU_ATTR1_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR1_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR1_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR1_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR1_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR1_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR1_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR1_XN
Instruction Access Disable
28
29
NVICMPU_ATTR2
MPU Region Attribute and Size Alias 2
0xDB0
read-write
n
0x0
0x0
NVIC_MPU_ATTR2_AP
Access Privilege
24
27
NVIC_MPU_ATTR2_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR2_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR2_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR2_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR2_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR2_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR2_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR2_XN
Instruction Access Disable
28
29
NVICMPU_ATTR3
MPU Region Attribute and Size Alias 3
0xDB8
read-write
n
0x0
0x0
NVIC_MPU_ATTR3_AP
Access Privilege
24
27
NVIC_MPU_ATTR3_BUFFRABLE
Bufferable
16
17
NVIC_MPU_ATTR3_CACHEABLE
Cacheable
17
18
NVIC_MPU_ATTR3_ENABLE
Region Enable
0
1
NVIC_MPU_ATTR3_SHAREABLE
Shareable
18
19
NVIC_MPU_ATTR3_SIZE
Region Size Mask
1
6
NVIC_MPU_ATTR3_SRD
Subregion Disable Bits
8
16
NVIC_MPU_ATTR3_TEX
Type Extension Mask
19
22
NVIC_MPU_ATTR3_XN
Instruction Access Disable
28
29
NVICMPU_BASE
MPU Region Base Address
0xD9C
read-write
n
0x0
0x0
NVIC_MPU_BASE_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE_REGION
Region Number
0
3
NVIC_MPU_BASE_VALID
Region Number Valid
4
5
NVICMPU_BASE1
MPU Region Base Address Alias 1
0xDA4
read-write
n
0x0
0x0
NVIC_MPU_BASE1_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE1_REGION
Region Number
0
3
NVIC_MPU_BASE1_VALID
Region Number Valid
4
5
NVICMPU_BASE2
MPU Region Base Address Alias 2
0xDAC
read-write
n
0x0
0x0
NVIC_MPU_BASE2_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE2_REGION
Region Number
0
3
NVIC_MPU_BASE2_VALID
Region Number Valid
4
5
NVICMPU_BASE3
MPU Region Base Address Alias 3
0xDB4
read-write
n
0x0
0x0
NVIC_MPU_BASE3_ADDR
Base Address Mask
5
32
NVIC_MPU_BASE3_REGION
Region Number
0
3
NVIC_MPU_BASE3_VALID
Region Number Valid
4
5
NVICMPU_CTRL
MPU Control
0xD94
read-write
n
0x0
0x0
NVIC_MPU_CTRL_ENABLE
MPU Enable
0
1
NVIC_MPU_CTRL_HFNMIENA
MPU Enabled During Faults
1
2
NVIC_MPU_CTRL_PRIVDEFEN
MPU Default Region
2
3
NVICMPU_NUMBER
MPU Region Number
0xD98
read-write
n
0x0
0x0
NVIC_MPU_NUMBER
MPU Region to Access
0
3
NVICMPU_TYPE
MPU Type
0xD90
read-write
n
0x0
0x0
NVIC_MPU_TYPE_DREGION
Number of D Regions
8
16
NVIC_MPU_TYPE_IREGION
Number of I Regions
16
24
NVIC_MPU_TYPE_SEPARATE
Separate or Unified MPU
0
1
NVICPEND0
Interrupt 0-31 Set Pending
0x200
read-write
n
0x0
0x0
NVIC_PEND0_INT
Interrupt Set Pending
0
32
NVIC_PEND0_INT0
Interrupt 0 pend
0x1
NVIC_PEND0_INT4
Interrupt 4 pend
0x10
NVIC_PEND0_INT8
Interrupt 8 pend
0x100
NVIC_PEND0_INT12
Interrupt 12 pend
0x1000
NVIC_PEND0_INT16
Interrupt 16 pend
0x10000
NVIC_PEND0_INT20
Interrupt 20 pend
0x100000
NVIC_PEND0_INT24
Interrupt 24 pend
0x1000000
NVIC_PEND0_INT28
Interrupt 28 pend
0x10000000
NVIC_PEND0_INT1
Interrupt 1 pend
0x2
NVIC_PEND0_INT5
Interrupt 5 pend
0x20
NVIC_PEND0_INT9
Interrupt 9 pend
0x200
NVIC_PEND0_INT13
Interrupt 13 pend
0x2000
NVIC_PEND0_INT17
Interrupt 17 pend
0x20000
NVIC_PEND0_INT21
Interrupt 21 pend
0x200000
NVIC_PEND0_INT25
Interrupt 25 pend
0x2000000
NVIC_PEND0_INT29
Interrupt 29 pend
0x20000000
NVIC_PEND0_INT2
Interrupt 2 pend
0x4
NVIC_PEND0_INT6
Interrupt 6 pend
0x40
NVIC_PEND0_INT10
Interrupt 10 pend
0x400
NVIC_PEND0_INT14
Interrupt 14 pend
0x4000
NVIC_PEND0_INT18
Interrupt 18 pend
0x40000
NVIC_PEND0_INT22
Interrupt 22 pend
0x400000
NVIC_PEND0_INT26
Interrupt 26 pend
0x4000000
NVIC_PEND0_INT30
Interrupt 30 pend
0x40000000
NVIC_PEND0_INT3
Interrupt 3 pend
0x8
NVIC_PEND0_INT7
Interrupt 7 pend
0x80
NVIC_PEND0_INT11
Interrupt 11 pend
0x800
NVIC_PEND0_INT15
Interrupt 15 pend
0x8000
NVIC_PEND0_INT19
Interrupt 19 pend
0x80000
NVIC_PEND0_INT23
Interrupt 23 pend
0x800000
NVIC_PEND0_INT27
Interrupt 27 pend
0x8000000
NVIC_PEND0_INT31
Interrupt 31 pend
0x80000000
NVICPEND1
Interrupt 32-54 Set Pending
0x204
read-write
n
0x0
0x0
NVIC_PEND1_INT
Interrupt Set Pending
0
16
NVIC_PEND1_INT32
Interrupt 32 pend
0x1
NVIC_PEND1_INT36
Interrupt 36 pend
0x10
NVIC_PEND1_INT40
Interrupt 40 pend
0x100
NVIC_PEND1_INT44
Interrupt 44 pend
0x1000
NVIC_PEND1_INT33
Interrupt 33 pend
0x2
NVIC_PEND1_INT37
Interrupt 37 pend
0x20
NVIC_PEND1_INT41
Interrupt 41 pend
0x200
NVIC_PEND1_INT45
Interrupt 45 pend
0x2000
NVIC_PEND1_INT34
Interrupt 34 pend
0x4
NVIC_PEND1_INT38
Interrupt 38 pend
0x40
NVIC_PEND1_INT42
Interrupt 42 pend
0x400
NVIC_PEND1_INT46
Interrupt 46 pend
0x4000
NVIC_PEND1_INT35
Interrupt 35 pend
0x8
NVIC_PEND1_INT39
Interrupt 39 pend
0x80
NVIC_PEND1_INT43
Interrupt 43 pend
0x800
NVIC_PEND1_INT47
Interrupt 47 pend
0x8000
NVICPRI0
Interrupt 0-3 Priority
0x400
read-write
n
0x0
0x0
NVIC_PRI0_INT0
Interrupt 0 Priority Mask
5
8
NVIC_PRI0_INT1
Interrupt 1 Priority Mask
13
16
NVIC_PRI0_INT2
Interrupt 2 Priority Mask
21
24
NVIC_PRI0_INT3
Interrupt 3 Priority Mask
29
32
NVICPRI1
Interrupt 4-7 Priority
0x404
read-write
n
0x0
0x0
NVIC_PRI1_INT4
Interrupt 4 Priority Mask
5
8
NVIC_PRI1_INT5
Interrupt 5 Priority Mask
13
16
NVIC_PRI1_INT6
Interrupt 6 Priority Mask
21
24
NVIC_PRI1_INT7
Interrupt 7 Priority Mask
29
32
NVICPRI10
Interrupt 40-43 Priority
0x428
read-write
n
0x0
0x0
NVIC_PRI10_INT40
Interrupt 40 Priority Mask
5
8
NVIC_PRI10_INT41
Interrupt 41 Priority Mask
13
16
NVIC_PRI10_INT42
Interrupt 42 Priority Mask
21
24
NVIC_PRI10_INT43
Interrupt 43 Priority Mask
29
32
NVICPRI11
Interrupt 44-47 Priority
0x42C
read-write
n
0x0
0x0
NVIC_PRI11_INT44
Interrupt 44 Priority Mask
5
8
NVIC_PRI11_INT45
Interrupt 45 Priority Mask
13
16
NVIC_PRI11_INT46
Interrupt 46 Priority Mask
21
24
NVIC_PRI11_INT47
Interrupt 47 Priority Mask
29
32
NVICPRI2
Interrupt 8-11 Priority
0x408
read-write
n
0x0
0x0
NVIC_PRI2_INT10
Interrupt 10 Priority Mask
21
24
NVIC_PRI2_INT11
Interrupt 11 Priority Mask
29
32
NVIC_PRI2_INT8
Interrupt 8 Priority Mask
5
8
NVIC_PRI2_INT9
Interrupt 9 Priority Mask
13
16
NVICPRI3
Interrupt 12-15 Priority
0x40C
read-write
n
0x0
0x0
NVIC_PRI3_INT12
Interrupt 12 Priority Mask
5
8
NVIC_PRI3_INT13
Interrupt 13 Priority Mask
13
16
NVIC_PRI3_INT14
Interrupt 14 Priority Mask
21
24
NVIC_PRI3_INT15
Interrupt 15 Priority Mask
29
32
NVICPRI4
Interrupt 16-19 Priority
0x410
read-write
n
0x0
0x0
NVIC_PRI4_INT16
Interrupt 16 Priority Mask
5
8
NVIC_PRI4_INT17
Interrupt 17 Priority Mask
13
16
NVIC_PRI4_INT18
Interrupt 18 Priority Mask
21
24
NVIC_PRI4_INT19
Interrupt 19 Priority Mask
29
32
NVICPRI5
Interrupt 20-23 Priority
0x414
read-write
n
0x0
0x0
NVIC_PRI5_INT20
Interrupt 20 Priority Mask
5
8
NVIC_PRI5_INT21
Interrupt 21 Priority Mask
13
16
NVIC_PRI5_INT22
Interrupt 22 Priority Mask
21
24
NVIC_PRI5_INT23
Interrupt 23 Priority Mask
29
32
NVICPRI6
Interrupt 24-27 Priority
0x418
read-write
n
0x0
0x0
NVIC_PRI6_INT24
Interrupt 24 Priority Mask
5
8
NVIC_PRI6_INT25
Interrupt 25 Priority Mask
13
16
NVIC_PRI6_INT26
Interrupt 26 Priority Mask
21
24
NVIC_PRI6_INT27
Interrupt 27 Priority Mask
29
32
NVICPRI7
Interrupt 28-31 Priority
0x41C
read-write
n
0x0
0x0
NVIC_PRI7_INT28
Interrupt 28 Priority Mask
5
8
NVIC_PRI7_INT29
Interrupt 29 Priority Mask
13
16
NVIC_PRI7_INT30
Interrupt 30 Priority Mask
21
24
NVIC_PRI7_INT31
Interrupt 31 Priority Mask
29
32
NVICPRI8
Interrupt 32-35 Priority
0x420
read-write
n
0x0
0x0
NVIC_PRI8_INT32
Interrupt 32 Priority Mask
5
8
NVIC_PRI8_INT33
Interrupt 33 Priority Mask
13
16
NVIC_PRI8_INT34
Interrupt 34 Priority Mask
21
24
NVIC_PRI8_INT35
Interrupt 35 Priority Mask
29
32
NVICPRI9
Interrupt 36-39 Priority
0x424
read-write
n
0x0
0x0
NVIC_PRI9_INT36
Interrupt 36 Priority Mask
5
8
NVIC_PRI9_INT37
Interrupt 37 Priority Mask
13
16
NVIC_PRI9_INT38
Interrupt 38 Priority Mask
21
24
NVIC_PRI9_INT39
Interrupt 39 Priority Mask
29
32
NVICST_CAL
SysTick Calibration Value Reg
0x1C
read-write
n
0x0
0x0
NVIC_ST_CAL_NOREF
No reference clock
31
32
NVIC_ST_CAL_ONEMS
1ms reference value
0
24
NVIC_ST_CAL_SKEW
Clock skew
30
31
NVICST_CTRL
SysTick Control and Status Register
0x10
read-write
n
0x0
0x0
NVIC_ST_CTRL_CLK_SRC
Clock Source
2
3
NVIC_ST_CTRL_COUNT
Count Flag
16
17
NVIC_ST_CTRL_ENABLE
Enable
0
1
NVIC_ST_CTRL_INTEN
Interrupt Enable
1
2
NVICST_CURRENT
SysTick Current Value Register
0x18
read-write
n
0x0
0x0
NVIC_ST_CURRENT
Current Value
0
24
NVICST_RELOAD
SysTick Reload Value Register
0x14
read-write
n
0x0
0x0
NVIC_ST_RELOAD
Reload Value
0
24
NVICSW_TRIG
Software Trigger Interrupt
0xF00
write-only
n
0x0
0x0
NVIC_SW_TRIG_INTID
Interrupt ID
0
6
write-only
NVICSYS_CTRL
System Control
0xD10
read-write
n
0x0
0x0
NVIC_SYS_CTRL_SEVONPEND
Wake Up on Pending
4
5
NVIC_SYS_CTRL_SLEEPDEEP
Deep Sleep Enable
2
3
NVIC_SYS_CTRL_SLEEPEXIT
Sleep on ISR Exit
1
2
NVICSYS_HND_CTRL
System Handler Control and State
0xD24
read-write
n
0x0
0x0
NVIC_SYS_HND_CTRL_BUS
Bus Fault Enable
17
18
NVIC_SYS_HND_CTRL_BUSA
Bus Fault Active
1
2
NVIC_SYS_HND_CTRL_BUSP
Bus Fault Pending
14
15
NVIC_SYS_HND_CTRL_MEM
Memory Management Fault Enable
16
17
NVIC_SYS_HND_CTRL_MEMA
Memory Management Fault Active
0
1
NVIC_SYS_HND_CTRL_MEMP
Memory Management Fault Pending
13
14
NVIC_SYS_HND_CTRL_MON
Debug Monitor Active
8
9
NVIC_SYS_HND_CTRL_PNDSV
PendSV Exception Active
10
11
NVIC_SYS_HND_CTRL_SVC
SVC Call Pending
15
16
NVIC_SYS_HND_CTRL_SVCA
SVC Call Active
7
8
NVIC_SYS_HND_CTRL_TICK
SysTick Exception Active
11
12
NVIC_SYS_HND_CTRL_USAGE
Usage Fault Enable
18
19
NVIC_SYS_HND_CTRL_USAGEP
Usage Fault Pending
12
13
NVIC_SYS_HND_CTRL_USGA
Usage Fault Active
3
4
NVICSYS_PRI1
System Handler Priority 1
0xD18
read-write
n
0x0
0x0
NVIC_SYS_PRI1_BUS
Bus Fault Priority
13
16
NVIC_SYS_PRI1_MEM
Memory Management Fault Priority
5
8
NVIC_SYS_PRI1_USAGE
Usage Fault Priority
21
24
NVICSYS_PRI2
System Handler Priority 2
0xD1C
read-write
n
0x0
0x0
NVIC_SYS_PRI2_SVC
SVCall Priority
29
32
NVICSYS_PRI3
System Handler Priority 3
0xD20
read-write
n
0x0
0x0
NVIC_SYS_PRI3_DEBUG
Debug Priority
5
8
NVIC_SYS_PRI3_PENDSV
PendSV Priority
21
24
NVIC_SYS_PRI3_TICK
SysTick Exception Priority
29
32
NVICUNPEND0
Interrupt 0-31 Clear Pending
0x280
read-write
n
0x0
0x0
NVIC_UNPEND0_INT
Interrupt Clear Pending
0
32
NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x1
NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x10
NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x100
NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x1000
NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x10000
NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x100000
NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x1000000
NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x10000000
NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x2
NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x20
NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x200
NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x2000
NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x20000
NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x200000
NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x2000000
NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x20000000
NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x4
NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x40
NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x400
NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x4000
NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x40000
NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x400000
NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x4000000
NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x40000000
NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x8
NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x80
NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x800
NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x8000
NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x80000
NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x800000
NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x8000000
NVIC_UNPEND0_INT31
Interrupt 31 unpend
0x80000000
NVICUNPEND1
Interrupt 32-54 Clear Pending
0x284
read-write
n
0x0
0x0
NVIC_UNPEND1_INT
Interrupt Clear Pending
0
16
NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x1
NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x10
NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x100
NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x1000
NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x2
NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x20
NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x200
NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x2000
NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x4
NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x40
NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x400
NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x4000
NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x8
NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x80
NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x800
NVIC_UNPEND1_INT47
Interrupt 47 unpend
0x8000
NVICVTABLE
Vector Table Offset
0xD08
read-write
n
0x0
0x0
NVIC_VTABLE_BASE
Vector Table Base
29
30
NVIC_VTABLE_OFFSET
Vector Table Offset
8
29
PEND0
Interrupt 0-31 Set Pending
0x200
-1
read-write
n
0x0
0x0
NVIC_PEND0_INT
Interrupt Set Pending
0
32
NVIC_PEND0_INT0
Interrupt 0 pend
0x1
NVIC_PEND0_INT4
Interrupt 4 pend
0x10
NVIC_PEND0_INT8
Interrupt 8 pend
0x100
NVIC_PEND0_INT12
Interrupt 12 pend
0x1000
NVIC_PEND0_INT16
Interrupt 16 pend
0x10000
NVIC_PEND0_INT20
Interrupt 20 pend
0x100000
NVIC_PEND0_INT24
Interrupt 24 pend
0x1000000
NVIC_PEND0_INT28
Interrupt 28 pend
0x10000000
NVIC_PEND0_INT1
Interrupt 1 pend
0x2
NVIC_PEND0_INT5
Interrupt 5 pend
0x20
NVIC_PEND0_INT9
Interrupt 9 pend
0x200
NVIC_PEND0_INT13
Interrupt 13 pend
0x2000
NVIC_PEND0_INT17
Interrupt 17 pend
0x20000
NVIC_PEND0_INT21
Interrupt 21 pend
0x200000
NVIC_PEND0_INT25
Interrupt 25 pend
0x2000000
NVIC_PEND0_INT29
Interrupt 29 pend
0x20000000
NVIC_PEND0_INT2
Interrupt 2 pend
0x4
NVIC_PEND0_INT6
Interrupt 6 pend
0x40
NVIC_PEND0_INT10
Interrupt 10 pend
0x400
NVIC_PEND0_INT14
Interrupt 14 pend
0x4000
NVIC_PEND0_INT18
Interrupt 18 pend
0x40000
NVIC_PEND0_INT22
Interrupt 22 pend
0x400000
NVIC_PEND0_INT26
Interrupt 26 pend
0x4000000
NVIC_PEND0_INT30
Interrupt 30 pend
0x40000000
NVIC_PEND0_INT3
Interrupt 3 pend
0x8
NVIC_PEND0_INT7
Interrupt 7 pend
0x80
NVIC_PEND0_INT11
Interrupt 11 pend
0x800
NVIC_PEND0_INT15
Interrupt 15 pend
0x8000
NVIC_PEND0_INT19
Interrupt 19 pend
0x80000
NVIC_PEND0_INT23
Interrupt 23 pend
0x800000
NVIC_PEND0_INT27
Interrupt 27 pend
0x8000000
NVIC_PEND0_INT31
Interrupt 31 pend
0x80000000
PEND1
Interrupt 32-54 Set Pending
0x204
-1
read-write
n
0x0
0x0
NVIC_PEND1_INT
Interrupt Set Pending
0
16
NVIC_PEND1_INT32
Interrupt 32 pend
0x1
NVIC_PEND1_INT36
Interrupt 36 pend
0x10
NVIC_PEND1_INT40
Interrupt 40 pend
0x100
NVIC_PEND1_INT44
Interrupt 44 pend
0x1000
NVIC_PEND1_INT33
Interrupt 33 pend
0x2
NVIC_PEND1_INT37
Interrupt 37 pend
0x20
NVIC_PEND1_INT41
Interrupt 41 pend
0x200
NVIC_PEND1_INT45
Interrupt 45 pend
0x2000
NVIC_PEND1_INT34
Interrupt 34 pend
0x4
NVIC_PEND1_INT38
Interrupt 38 pend
0x40
NVIC_PEND1_INT42
Interrupt 42 pend
0x400
NVIC_PEND1_INT46
Interrupt 46 pend
0x4000
NVIC_PEND1_INT35
Interrupt 35 pend
0x8
NVIC_PEND1_INT39
Interrupt 39 pend
0x80
NVIC_PEND1_INT43
Interrupt 43 pend
0x800
NVIC_PEND1_INT47
Interrupt 47 pend
0x8000
PRI0
Interrupt 0-3 Priority
0x400
-1
read-write
n
0x0
0x0
NVIC_PRI0_INT0
Interrupt 0 Priority Mask
5
8
NVIC_PRI0_INT1
Interrupt 1 Priority Mask
13
16
NVIC_PRI0_INT2
Interrupt 2 Priority Mask
21
24
NVIC_PRI0_INT3
Interrupt 3 Priority Mask
29
32
PRI1
Interrupt 4-7 Priority
0x404
-1
read-write
n
0x0
0x0
NVIC_PRI1_INT4
Interrupt 4 Priority Mask
5
8
NVIC_PRI1_INT5
Interrupt 5 Priority Mask
13
16
NVIC_PRI1_INT6
Interrupt 6 Priority Mask
21
24
NVIC_PRI1_INT7
Interrupt 7 Priority Mask
29
32
PRI10
Interrupt 40-43 Priority
0x428
-1
read-write
n
0x0
0x0
NVIC_PRI10_INT40
Interrupt 40 Priority Mask
5
8
NVIC_PRI10_INT41
Interrupt 41 Priority Mask
13
16
NVIC_PRI10_INT42
Interrupt 42 Priority Mask
21
24
NVIC_PRI10_INT43
Interrupt 43 Priority Mask
29
32
PRI11
Interrupt 44-47 Priority
0x42C
-1
read-write
n
0x0
0x0
NVIC_PRI11_INT44
Interrupt 44 Priority Mask
5
8
NVIC_PRI11_INT45
Interrupt 45 Priority Mask
13
16
NVIC_PRI11_INT46
Interrupt 46 Priority Mask
21
24
NVIC_PRI11_INT47
Interrupt 47 Priority Mask
29
32
PRI2
Interrupt 8-11 Priority
0x408
-1
read-write
n
0x0
0x0
NVIC_PRI2_INT10
Interrupt 10 Priority Mask
21
24
NVIC_PRI2_INT11
Interrupt 11 Priority Mask
29
32
NVIC_PRI2_INT8
Interrupt 8 Priority Mask
5
8
NVIC_PRI2_INT9
Interrupt 9 Priority Mask
13
16
PRI3
Interrupt 12-15 Priority
0x40C
-1
read-write
n
0x0
0x0
NVIC_PRI3_INT12
Interrupt 12 Priority Mask
5
8
NVIC_PRI3_INT13
Interrupt 13 Priority Mask
13
16
NVIC_PRI3_INT14
Interrupt 14 Priority Mask
21
24
NVIC_PRI3_INT15
Interrupt 15 Priority Mask
29
32
PRI4
Interrupt 16-19 Priority
0x410
-1
read-write
n
0x0
0x0
NVIC_PRI4_INT16
Interrupt 16 Priority Mask
5
8
NVIC_PRI4_INT17
Interrupt 17 Priority Mask
13
16
NVIC_PRI4_INT18
Interrupt 18 Priority Mask
21
24
NVIC_PRI4_INT19
Interrupt 19 Priority Mask
29
32
PRI5
Interrupt 20-23 Priority
0x414
-1
read-write
n
0x0
0x0
NVIC_PRI5_INT20
Interrupt 20 Priority Mask
5
8
NVIC_PRI5_INT21
Interrupt 21 Priority Mask
13
16
NVIC_PRI5_INT22
Interrupt 22 Priority Mask
21
24
NVIC_PRI5_INT23
Interrupt 23 Priority Mask
29
32
PRI6
Interrupt 24-27 Priority
0x418
-1
read-write
n
0x0
0x0
NVIC_PRI6_INT24
Interrupt 24 Priority Mask
5
8
NVIC_PRI6_INT25
Interrupt 25 Priority Mask
13
16
NVIC_PRI6_INT26
Interrupt 26 Priority Mask
21
24
NVIC_PRI6_INT27
Interrupt 27 Priority Mask
29
32
PRI7
Interrupt 28-31 Priority
0x41C
-1
read-write
n
0x0
0x0
NVIC_PRI7_INT28
Interrupt 28 Priority Mask
5
8
NVIC_PRI7_INT29
Interrupt 29 Priority Mask
13
16
NVIC_PRI7_INT30
Interrupt 30 Priority Mask
21
24
NVIC_PRI7_INT31
Interrupt 31 Priority Mask
29
32
PRI8
Interrupt 32-35 Priority
0x420
-1
read-write
n
0x0
0x0
NVIC_PRI8_INT32
Interrupt 32 Priority Mask
5
8
NVIC_PRI8_INT33
Interrupt 33 Priority Mask
13
16
NVIC_PRI8_INT34
Interrupt 34 Priority Mask
21
24
NVIC_PRI8_INT35
Interrupt 35 Priority Mask
29
32
PRI9
Interrupt 36-39 Priority
0x424
-1
read-write
n
0x0
0x0
NVIC_PRI9_INT36
Interrupt 36 Priority Mask
5
8
NVIC_PRI9_INT37
Interrupt 37 Priority Mask
13
16
NVIC_PRI9_INT38
Interrupt 38 Priority Mask
21
24
NVIC_PRI9_INT39
Interrupt 39 Priority Mask
29
32
ST_CAL
SysTick Calibration Value Reg
0x1C
-1
read-write
n
0x0
0x0
NVIC_ST_CAL_NOREF
No reference clock
31
32
NVIC_ST_CAL_ONEMS
1ms reference value
0
24
NVIC_ST_CAL_SKEW
Clock skew
30
31
ST_CTRL
SysTick Control and Status Register
0x10
-1
read-write
n
0x0
0x0
NVIC_ST_CTRL_CLK_SRC
Clock Source
2
3
NVIC_ST_CTRL_COUNT
Count Flag
16
17
NVIC_ST_CTRL_ENABLE
Enable
0
1
NVIC_ST_CTRL_INTEN
Interrupt Enable
1
2
ST_CURRENT
SysTick Current Value Register
0x18
-1
read-write
n
0x0
0x0
NVIC_ST_CURRENT
Current Value
0
24
ST_RELOAD
SysTick Reload Value Register
0x14
-1
read-write
n
0x0
0x0
NVIC_ST_RELOAD
Reload Value
0
24
SW_TRIG
Software Trigger Interrupt
0xF00
-1
write-only
n
0x0
0x0
NVIC_SW_TRIG_INTID
Interrupt ID
0
6
write-only
SYS_CTRL
System Control
0xD10
-1
read-write
n
0x0
0x0
NVIC_SYS_CTRL_SEVONPEND
Wake Up on Pending
4
5
NVIC_SYS_CTRL_SLEEPDEEP
Deep Sleep Enable
2
3
NVIC_SYS_CTRL_SLEEPEXIT
Sleep on ISR Exit
1
2
SYS_HND_CTRL
System Handler Control and State
0xD24
-1
read-write
n
0x0
0x0
NVIC_SYS_HND_CTRL_BUS
Bus Fault Enable
17
18
NVIC_SYS_HND_CTRL_BUSA
Bus Fault Active
1
2
NVIC_SYS_HND_CTRL_BUSP
Bus Fault Pending
14
15
NVIC_SYS_HND_CTRL_MEM
Memory Management Fault Enable
16
17
NVIC_SYS_HND_CTRL_MEMA
Memory Management Fault Active
0
1
NVIC_SYS_HND_CTRL_MEMP
Memory Management Fault Pending
13
14
NVIC_SYS_HND_CTRL_MON
Debug Monitor Active
8
9
NVIC_SYS_HND_CTRL_PNDSV
PendSV Exception Active
10
11
NVIC_SYS_HND_CTRL_SVC
SVC Call Pending
15
16
NVIC_SYS_HND_CTRL_SVCA
SVC Call Active
7
8
NVIC_SYS_HND_CTRL_TICK
SysTick Exception Active
11
12
NVIC_SYS_HND_CTRL_USAGE
Usage Fault Enable
18
19
NVIC_SYS_HND_CTRL_USAGEP
Usage Fault Pending
12
13
NVIC_SYS_HND_CTRL_USGA
Usage Fault Active
3
4
SYS_PRI1
System Handler Priority 1
0xD18
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI1_BUS
Bus Fault Priority
13
16
NVIC_SYS_PRI1_MEM
Memory Management Fault Priority
5
8
NVIC_SYS_PRI1_USAGE
Usage Fault Priority
21
24
SYS_PRI2
System Handler Priority 2
0xD1C
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI2_SVC
SVCall Priority
29
32
SYS_PRI3
System Handler Priority 3
0xD20
-1
read-write
n
0x0
0x0
NVIC_SYS_PRI3_DEBUG
Debug Priority
5
8
NVIC_SYS_PRI3_PENDSV
PendSV Priority
21
24
NVIC_SYS_PRI3_TICK
SysTick Exception Priority
29
32
UNPEND0
Interrupt 0-31 Clear Pending
0x280
-1
read-write
n
0x0
0x0
NVIC_UNPEND0_INT
Interrupt Clear Pending
0
32
NVIC_UNPEND0_INT0
Interrupt 0 unpend
0x1
NVIC_UNPEND0_INT4
Interrupt 4 unpend
0x10
NVIC_UNPEND0_INT8
Interrupt 8 unpend
0x100
NVIC_UNPEND0_INT12
Interrupt 12 unpend
0x1000
NVIC_UNPEND0_INT16
Interrupt 16 unpend
0x10000
NVIC_UNPEND0_INT20
Interrupt 20 unpend
0x100000
NVIC_UNPEND0_INT24
Interrupt 24 unpend
0x1000000
NVIC_UNPEND0_INT28
Interrupt 28 unpend
0x10000000
NVIC_UNPEND0_INT1
Interrupt 1 unpend
0x2
NVIC_UNPEND0_INT5
Interrupt 5 unpend
0x20
NVIC_UNPEND0_INT9
Interrupt 9 unpend
0x200
NVIC_UNPEND0_INT13
Interrupt 13 unpend
0x2000
NVIC_UNPEND0_INT17
Interrupt 17 unpend
0x20000
NVIC_UNPEND0_INT21
Interrupt 21 unpend
0x200000
NVIC_UNPEND0_INT25
Interrupt 25 unpend
0x2000000
NVIC_UNPEND0_INT29
Interrupt 29 unpend
0x20000000
NVIC_UNPEND0_INT2
Interrupt 2 unpend
0x4
NVIC_UNPEND0_INT6
Interrupt 6 unpend
0x40
NVIC_UNPEND0_INT10
Interrupt 10 unpend
0x400
NVIC_UNPEND0_INT14
Interrupt 14 unpend
0x4000
NVIC_UNPEND0_INT18
Interrupt 18 unpend
0x40000
NVIC_UNPEND0_INT22
Interrupt 22 unpend
0x400000
NVIC_UNPEND0_INT26
Interrupt 26 unpend
0x4000000
NVIC_UNPEND0_INT30
Interrupt 30 unpend
0x40000000
NVIC_UNPEND0_INT3
Interrupt 3 unpend
0x8
NVIC_UNPEND0_INT7
Interrupt 7 unpend
0x80
NVIC_UNPEND0_INT11
Interrupt 11 unpend
0x800
NVIC_UNPEND0_INT15
Interrupt 15 unpend
0x8000
NVIC_UNPEND0_INT19
Interrupt 19 unpend
0x80000
NVIC_UNPEND0_INT23
Interrupt 23 unpend
0x800000
NVIC_UNPEND0_INT27
Interrupt 27 unpend
0x8000000
NVIC_UNPEND0_INT31
Interrupt 31 unpend
0x80000000
UNPEND1
Interrupt 32-54 Clear Pending
0x284
-1
read-write
n
0x0
0x0
NVIC_UNPEND1_INT
Interrupt Clear Pending
0
16
NVIC_UNPEND1_INT32
Interrupt 32 unpend
0x1
NVIC_UNPEND1_INT36
Interrupt 36 unpend
0x10
NVIC_UNPEND1_INT40
Interrupt 40 unpend
0x100
NVIC_UNPEND1_INT44
Interrupt 44 unpend
0x1000
NVIC_UNPEND1_INT33
Interrupt 33 unpend
0x2
NVIC_UNPEND1_INT37
Interrupt 37 unpend
0x20
NVIC_UNPEND1_INT41
Interrupt 41 unpend
0x200
NVIC_UNPEND1_INT45
Interrupt 45 unpend
0x2000
NVIC_UNPEND1_INT34
Interrupt 34 unpend
0x4
NVIC_UNPEND1_INT38
Interrupt 38 unpend
0x40
NVIC_UNPEND1_INT42
Interrupt 42 unpend
0x400
NVIC_UNPEND1_INT46
Interrupt 46 unpend
0x4000
NVIC_UNPEND1_INT35
Interrupt 35 unpend
0x8
NVIC_UNPEND1_INT39
Interrupt 39 unpend
0x80
NVIC_UNPEND1_INT43
Interrupt 43 unpend
0x800
NVIC_UNPEND1_INT47
Interrupt 47 unpend
0x8000
VTABLE
Vector Table Offset
0xD08
-1
read-write
n
0x0
0x0
NVIC_VTABLE_BASE
Vector Table Base
29
30
NVIC_VTABLE_OFFSET
Vector Table Offset
8
29
PWM0
Register map for PWM0 peripheral
PWM
0x0
0x0
0x1000
registers
n
0_CMPA
PWM0 Compare A
0x58
read-write
n
0x0
0x0
PWM_X_CMPA
Comparator A Value
0
16
0_CMPB
PWM0 Compare B
0x5C
read-write
n
0x0
0x0
PWM_X_CMPB
Comparator B Value
0
16
0_COUNT
PWM0 Counter
0x54
read-write
n
0x0
0x0
PWM_X_COUNT
Counter Value
0
16
0_CTL
PWM0 Control
0x40
read-write
n
0x0
0x0
PWM_X_CTL_CMPAUPD
Comparator A Update Mode
4
5
PWM_X_CTL_CMPBUPD
Comparator B Update Mode
5
6
PWM_X_CTL_DBCTLUPD
PWMnDBCTL Update Mode
10
12
PWM_X_CTL_DBCTLUPD_I
Immediate
0x0
PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBFALLUPD
PWMnDBFALL Update Mode
14
16
PWM_X_CTL_DBFALLUPD_I
Immediate
0x0
PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBRISEUPD
PWMnDBRISE Update Mode
12
14
PWM_X_CTL_DBRISEUPD_I
Immediate
0x0
PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DEBUG
Debug Mode
2
3
PWM_X_CTL_ENABLE
PWM Block Enable
0
1
PWM_X_CTL_GENAUPD
PWMnGENA Update Mode
6
8
PWM_X_CTL_GENAUPD_I
Immediate
0x0
PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENAUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_GENBUPD
PWMnGENB Update Mode
8
10
PWM_X_CTL_GENBUPD_I
Immediate
0x0
PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENBUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_LOADUPD
Load Register Update Mode
3
4
PWM_X_CTL_MODE
Counter Mode
1
2
0_DBCTL
PWM0 Dead-Band Control
0x68
read-write
n
0x0
0x0
PWM_X_DBCTL_ENABLE
Dead-Band Generator Enable
0
1
0_DBFALL
PWM0 Dead-Band Falling-Edge-Delay
0x70
read-write
n
0x0
0x0
PWM_X_DBFALL_DELAY
Dead-Band Fall Delay
0
12
0_DBRISE
PWM0 Dead-Band Rising-Edge Delay
0x6C
read-write
n
0x0
0x0
PWM_X_DBRISE_DELAY
Dead-Band Rise Delay
0
12
0_FLTSEN
PWM0 Fault Pin Logic Sense
0x800
read-write
n
0x0
0x0
PWM_X_FLTSEN_FAULT0
Fault0 Sense
0
1
0_FLTSRC0
PWM0 Fault Source 0
0x74
read-write
n
0x0
0x0
PWM_X_FLTSRC0_FAULT0
Fault0 Input
0
1
0_FLTSTAT0
PWM0 Fault Status 0
0x804
read-only
n
0x0
0x0
PWM_X_FLTSTAT0_FAULT0
Fault Input 0
0
1
read-only
0_GENA
PWM0 Generator A Control
0x60
read-write
n
0x0
0x0
PWM_X_GENA_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTZERO
Action for Counter=0
0
2
PWM_X_GENA_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x1
PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
0x3
0_GENB
PWM0 Generator B Control
0x64
read-write
n
0x0
0x0
PWM_X_GENB_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTZERO
Action for Counter=0
0
2
PWM_X_GENB_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x1
PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
0x3
0_INTEN
PWM0 Interrupt and Trigger Enable
0x44
read-write
n
0x0
0x0
PWM_X_INTEN_INTCMPAD
Interrupt for Counter=PWMnCMPA Down
3
4
PWM_X_INTEN_INTCMPAU
Interrupt for Counter=PWMnCMPA Up
2
3
PWM_X_INTEN_INTCMPBD
Interrupt for Counter=PWMnCMPB Down
5
6
PWM_X_INTEN_INTCMPBU
Interrupt for Counter=PWMnCMPB Up
4
5
PWM_X_INTEN_INTCNTLOAD
Interrupt for Counter=PWMnLOAD
1
2
PWM_X_INTEN_INTCNTZERO
Interrupt for Counter=0
0
1
PWM_X_INTEN_TRCMPAD
Trigger for Counter=PWMnCMPA Down
11
12
PWM_X_INTEN_TRCMPAU
Trigger for Counter=PWMnCMPA Up
10
11
PWM_X_INTEN_TRCMPBD
Trigger for Counter=PWMnCMPB Down
13
14
PWM_X_INTEN_TRCMPBU
Trigger for Counter=PWMnCMPB Up
12
13
PWM_X_INTEN_TRCNTLOAD
Trigger for Counter=PWMnLOAD
9
10
PWM_X_INTEN_TRCNTZERO
Trigger for Counter=0
8
9
0_ISC
PWM0 Interrupt Status and Clear
0x4C
read-write
n
0x0
0x0
PWM_X_ISC_INTCMPAD
Comparator A Down Interrupt
3
4
PWM_X_ISC_INTCMPAU
Comparator A Up Interrupt
2
3
PWM_X_ISC_INTCMPBD
Comparator B Down Interrupt
5
6
PWM_X_ISC_INTCMPBU
Comparator B Up Interrupt
4
5
PWM_X_ISC_INTCNTLOAD
Counter=Load Interrupt
1
2
PWM_X_ISC_INTCNTZERO
Counter=0 Interrupt
0
1
0_LOAD
PWM0 Load
0x50
read-write
n
0x0
0x0
PWM_X_LOAD
Counter Load Value
0
16
0_RIS
PWM0 Raw Interrupt Status
0x48
read-write
n
0x0
0x0
PWM_X_RIS_INTCMPAD
Comparator A Down Interrupt Status
3
4
PWM_X_RIS_INTCMPAU
Comparator A Up Interrupt Status
2
3
PWM_X_RIS_INTCMPBD
Comparator B Down Interrupt Status
5
6
PWM_X_RIS_INTCMPBU
Comparator B Up Interrupt Status
4
5
PWM_X_RIS_INTCNTLOAD
Counter=Load Interrupt Status
1
2
PWM_X_RIS_INTCNTZERO
Counter=0 Interrupt Status
0
1
CTL
PWM Master Control
0x0
-1
read-write
n
0x0
0x0
PWM_CTL_GLOBALSYNC0
Update PWM Generator 0
0
1
ENABLE
PWM Output Enable
0x8
-1
read-write
n
0x0
0x0
PWM_ENABLE_PWM0EN
PWM0 Output Enable
0
1
PWM_ENABLE_PWM1EN
PWM1 Output Enable
1
2
FAULT
PWM Output Fault
0x10
-1
read-write
n
0x0
0x0
PWM_FAULT_FAULT0
PWM0 Fault
0
1
PWM_FAULT_FAULT1
PWM1 Fault
1
2
INTEN
PWM Interrupt Enable
0x14
-1
read-write
n
0x0
0x0
PWM_INTEN_INTFAULT0
Interrupt Fault 0
16
17
PWM_INTEN_INTPWM0
PWM0 Interrupt Enable
0
1
INVERT
PWM Output Inversion
0xC
-1
read-write
n
0x0
0x0
PWM_INVERT_PWM0INV
Invert PWM0 Signal
0
1
PWM_INVERT_PWM1INV
Invert PWM1 Signal
1
2
ISC
PWM Interrupt Status and Clear
0x1C
-1
read-write
n
0x0
0x0
PWM_ISC_INTFAULT0
FAULT0 Interrupt Asserted
16
17
PWM_ISC_INTPWM0
PWM0 Interrupt Status
0
1
PWM0CTL
PWM Master Control
0x0
read-write
n
0x0
0x0
PWM_CTL_GLOBALSYNC0
Update PWM Generator 0
0
1
PWM0ENABLE
PWM Output Enable
0x8
read-write
n
0x0
0x0
PWM_ENABLE_PWM0EN
PWM0 Output Enable
0
1
PWM_ENABLE_PWM1EN
PWM1 Output Enable
1
2
PWM0FAULT
PWM Output Fault
0x10
read-write
n
0x0
0x0
PWM_FAULT_FAULT0
PWM0 Fault
0
1
PWM_FAULT_FAULT1
PWM1 Fault
1
2
PWM0INTEN
PWM Interrupt Enable
0x14
read-write
n
0x0
0x0
PWM_INTEN_INTFAULT0
Interrupt Fault 0
16
17
PWM_INTEN_INTPWM0
PWM0 Interrupt Enable
0
1
PWM0INVERT
PWM Output Inversion
0xC
read-write
n
0x0
0x0
PWM_INVERT_PWM0INV
Invert PWM0 Signal
0
1
PWM_INVERT_PWM1INV
Invert PWM1 Signal
1
2
PWM0ISC
PWM Interrupt Status and Clear
0x1C
read-write
n
0x0
0x0
PWM_ISC_INTFAULT0
FAULT0 Interrupt Asserted
16
17
PWM_ISC_INTPWM0
PWM0 Interrupt Status
0
1
PWM0RIS
PWM Raw Interrupt Status
0x18
read-write
n
0x0
0x0
PWM_RIS_INTFAULT0
Interrupt Fault PWM 0
16
17
PWM_RIS_INTPWM0
PWM0 Interrupt Asserted
0
1
PWM0STATUS
PWM Status
0x20
read-write
n
0x0
0x0
PWM_STATUS_FAULT0
Generator 0 Fault Status
0
1
PWM0SYNC
PWM Time Base Sync
0x4
read-write
n
0x0
0x0
PWM_SYNC_SYNC0
Reset Generator 0 Counter
0
1
RIS
PWM Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
PWM_RIS_INTFAULT0
Interrupt Fault PWM 0
16
17
PWM_RIS_INTPWM0
PWM0 Interrupt Asserted
0
1
STATUS
PWM Status
0x20
-1
read-write
n
0x0
0x0
PWM_STATUS_FAULT0
Generator 0 Fault Status
0
1
SYNC
PWM Time Base Sync
0x4
-1
read-write
n
0x0
0x0
PWM_SYNC_SYNC0
Reset Generator 0 Counter
0
1
_0_CMPA
PWM0 Compare A
0x58
-1
read-write
n
0x0
0x0
PWM_X_CMPA
Comparator A Value
0
16
_0_CMPB
PWM0 Compare B
0x5C
-1
read-write
n
0x0
0x0
PWM_X_CMPB
Comparator B Value
0
16
_0_COUNT
PWM0 Counter
0x54
-1
read-write
n
0x0
0x0
PWM_X_COUNT
Counter Value
0
16
_0_CTL
PWM0 Control
0x40
-1
read-write
n
0x0
0x0
PWM_X_CTL_CMPAUPD
Comparator A Update Mode
4
5
PWM_X_CTL_CMPBUPD
Comparator B Update Mode
5
6
PWM_X_CTL_DBCTLUPD
PWMnDBCTL Update Mode
10
12
PWM_X_CTL_DBCTLUPD_I
Immediate
0x0
PWM_X_CTL_DBCTLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBCTLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBFALLUPD
PWMnDBFALL Update Mode
14
16
PWM_X_CTL_DBFALLUPD_I
Immediate
0x0
PWM_X_CTL_DBFALLUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBFALLUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DBRISEUPD
PWMnDBRISE Update Mode
12
14
PWM_X_CTL_DBRISEUPD_I
Immediate
0x0
PWM_X_CTL_DBRISEUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_DBRISEUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_DEBUG
Debug Mode
2
3
PWM_X_CTL_ENABLE
PWM Block Enable
0
1
PWM_X_CTL_GENAUPD
PWMnGENA Update Mode
6
8
PWM_X_CTL_GENAUPD_I
Immediate
0x0
PWM_X_CTL_GENAUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENAUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_GENBUPD
PWMnGENB Update Mode
8
10
PWM_X_CTL_GENBUPD_I
Immediate
0x0
PWM_X_CTL_GENBUPD_LS
Locally Synchronized
0x2
PWM_X_CTL_GENBUPD_GS
Globally Synchronized
0x3
PWM_X_CTL_LOADUPD
Load Register Update Mode
3
4
PWM_X_CTL_MODE
Counter Mode
1
2
_0_DBCTL
PWM0 Dead-Band Control
0x68
-1
read-write
n
0x0
0x0
PWM_X_DBCTL_ENABLE
Dead-Band Generator Enable
0
1
_0_DBFALL
PWM0 Dead-Band Falling-Edge-Delay
0x70
-1
read-write
n
0x0
0x0
PWM_X_DBFALL_DELAY
Dead-Band Fall Delay
0
12
_0_DBRISE
PWM0 Dead-Band Rising-Edge Delay
0x6C
-1
read-write
n
0x0
0x0
PWM_X_DBRISE_DELAY
Dead-Band Rise Delay
0
12
_0_FLTSEN
PWM0 Fault Pin Logic Sense
0x800
-1
read-write
n
0x0
0x0
PWM_X_FLTSEN_FAULT0
Fault0 Sense
0
1
_0_FLTSRC0
PWM0 Fault Source 0
0x74
-1
read-write
n
0x0
0x0
PWM_X_FLTSRC0_FAULT0
Fault0 Input
0
1
_0_FLTSTAT0
PWM0 Fault Status 0
0x804
-1
read-only
n
0x0
0x0
PWM_X_FLTSTAT0_FAULT0
Fault Input 0
0
1
read-only
_0_GENA
PWM0 Generator A Control
0x60
-1
read-write
n
0x0
0x0
PWM_X_GENA_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENA_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENA_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPAU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPAU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPAU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENA_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENA_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENA_ACTCMPBU_INV
Invert pwmA
0x1
PWM_X_GENA_ACTCMPBU_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTCMPBU_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENA_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENA_ACTLOAD_INV
Invert pwmA
0x1
PWM_X_GENA_ACTLOAD_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTLOAD_ONE
Drive pwmA High
0x3
PWM_X_GENA_ACTZERO
Action for Counter=0
0
2
PWM_X_GENA_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENA_ACTZERO_INV
Invert pwmA
0x1
PWM_X_GENA_ACTZERO_ZERO
Drive pwmA Low
0x2
PWM_X_GENA_ACTZERO_ONE
Drive pwmA High
0x3
_0_GENB
PWM0 Generator B Control
0x64
-1
read-write
n
0x0
0x0
PWM_X_GENB_ACTCMPAD
Action for Comparator A Down
6
8
PWM_X_GENB_ACTCMPAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPAU
Action for Comparator A Up
4
6
PWM_X_GENB_ACTCMPAU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPAU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPAU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPAU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBD
Action for Comparator B Down
10
12
PWM_X_GENB_ACTCMPBD_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTCMPBU
Action for Comparator B Up
8
10
PWM_X_GENB_ACTCMPBU_NONE
Do nothing
0x0
PWM_X_GENB_ACTCMPBU_INV
Invert pwmB
0x1
PWM_X_GENB_ACTCMPBU_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTCMPBU_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTLOAD
Action for Counter=LOAD
2
4
PWM_X_GENB_ACTLOAD_NONE
Do nothing
0x0
PWM_X_GENB_ACTLOAD_INV
Invert pwmB
0x1
PWM_X_GENB_ACTLOAD_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTLOAD_ONE
Drive pwmB High
0x3
PWM_X_GENB_ACTZERO
Action for Counter=0
0
2
PWM_X_GENB_ACTZERO_NONE
Do nothing
0x0
PWM_X_GENB_ACTZERO_INV
Invert pwmB
0x1
PWM_X_GENB_ACTZERO_ZERO
Drive pwmB Low
0x2
PWM_X_GENB_ACTZERO_ONE
Drive pwmB High
0x3
_0_INTEN
PWM0 Interrupt and Trigger Enable
0x44
-1
read-write
n
0x0
0x0
PWM_X_INTEN_INTCMPAD
Interrupt for Counter=PWMnCMPA Down
3
4
PWM_X_INTEN_INTCMPAU
Interrupt for Counter=PWMnCMPA Up
2
3
PWM_X_INTEN_INTCMPBD
Interrupt for Counter=PWMnCMPB Down
5
6
PWM_X_INTEN_INTCMPBU
Interrupt for Counter=PWMnCMPB Up
4
5
PWM_X_INTEN_INTCNTLOAD
Interrupt for Counter=PWMnLOAD
1
2
PWM_X_INTEN_INTCNTZERO
Interrupt for Counter=0
0
1
PWM_X_INTEN_TRCMPAD
Trigger for Counter=PWMnCMPA Down
11
12
PWM_X_INTEN_TRCMPAU
Trigger for Counter=PWMnCMPA Up
10
11
PWM_X_INTEN_TRCMPBD
Trigger for Counter=PWMnCMPB Down
13
14
PWM_X_INTEN_TRCMPBU
Trigger for Counter=PWMnCMPB Up
12
13
PWM_X_INTEN_TRCNTLOAD
Trigger for Counter=PWMnLOAD
9
10
PWM_X_INTEN_TRCNTZERO
Trigger for Counter=0
8
9
_0_ISC
PWM0 Interrupt Status and Clear
0x4C
-1
read-write
n
0x0
0x0
PWM_X_ISC_INTCMPAD
Comparator A Down Interrupt
3
4
PWM_X_ISC_INTCMPAU
Comparator A Up Interrupt
2
3
PWM_X_ISC_INTCMPBD
Comparator B Down Interrupt
5
6
PWM_X_ISC_INTCMPBU
Comparator B Up Interrupt
4
5
PWM_X_ISC_INTCNTLOAD
Counter=Load Interrupt
1
2
PWM_X_ISC_INTCNTZERO
Counter=0 Interrupt
0
1
_0_LOAD
PWM0 Load
0x50
-1
read-write
n
0x0
0x0
PWM_X_LOAD
Counter Load Value
0
16
_0_RIS
PWM0 Raw Interrupt Status
0x48
-1
read-write
n
0x0
0x0
PWM_X_RIS_INTCMPAD
Comparator A Down Interrupt Status
3
4
PWM_X_RIS_INTCMPAU
Comparator A Up Interrupt Status
2
3
PWM_X_RIS_INTCMPBD
Comparator B Down Interrupt Status
5
6
PWM_X_RIS_INTCMPBU
Comparator B Up Interrupt Status
4
5
PWM_X_RIS_INTCNTLOAD
Counter=Load Interrupt Status
1
2
PWM_X_RIS_INTCNTZERO
Counter=0 Interrupt Status
0
1
SSI0
Register map for SSI0 peripheral
SSI
0x0
0x0
0x1000
registers
n
CPSR
SSI Clock Prescale
0x10
-1
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
CR0
SSI Control 0
0x0
-1
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
CR1
SSI Control 1
0x4
-1
read-write
n
0x0
0x0
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
DMACTL
SSI DMA Control
0x24
-1
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
SSI Data
0x8
-1
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
ICR
SSI Interrupt Clear
0x20
-1
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
IM
SSI Interrupt Mask
0x14
-1
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
MIS
SSI Masked Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
RIS
SSI Raw Interrupt Status
0x18
-1
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SR
SSI Status
0xC
-1
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SSI0CPSR
SSI Clock Prescale
0x10
read-write
n
0x0
0x0
SSI_CPSR_CPSDVSR
SSI Clock Prescale Divisor
0
8
SSI0CR0
SSI Control 0
0x0
read-write
n
0x0
0x0
SSI_CR0_DSS
SSI Data Size Select
0
4
SSI_CR0_DSS_4
4-bit data
0x3
SSI_CR0_DSS_5
5-bit data
0x4
SSI_CR0_DSS_6
6-bit data
0x5
SSI_CR0_DSS_7
7-bit data
0x6
SSI_CR0_DSS_8
8-bit data
0x7
SSI_CR0_DSS_9
9-bit data
0x8
SSI_CR0_DSS_10
10-bit data
0x9
SSI_CR0_DSS_11
11-bit data
0xa
SSI_CR0_DSS_12
12-bit data
0xb
SSI_CR0_DSS_13
13-bit data
0xc
SSI_CR0_DSS_14
14-bit data
0xd
SSI_CR0_DSS_15
15-bit data
0xe
SSI_CR0_DSS_16
16-bit data
0xf
SSI_CR0_FRF
SSI Frame Format Select
4
6
SSI_CR0_FRF_MOTO
Freescale SPI Frame Format
0x0
SSI_CR0_FRF_TI
Texas Instruments Synchronous Serial Frame Format
0x1
SSI_CR0_FRF_NMW
MICROWIRE Frame Format
0x2
SSI_CR0_SCR
SSI Serial Clock Rate
8
16
SSI_CR0_SPH
SSI Serial Clock Phase
7
8
SSI_CR0_SPO
SSI Serial Clock Polarity
6
7
SSI0CR1
SSI Control 1
0x4
read-write
n
0x0
0x0
SSI_CR1_LBM
SSI Loopback Mode
0
1
SSI_CR1_MS
SSI Master/Slave Select
2
3
SSI_CR1_SOD
SSI Slave Mode Output Disable
3
4
SSI_CR1_SSE
SSI Synchronous Serial Port Enable
1
2
SSI0DMACTL
SSI DMA Control
0x24
read-write
n
0x0
0x0
SSI_DMACTL_RXDMAE
Receive DMA Enable
0
1
SSI_DMACTL_TXDMAE
Transmit DMA Enable
1
2
SSI0DR
SSI Data
0x8
read-write
n
0x0
0x0
SSI_DR_DATA
SSI Receive/Transmit Data
0
16
SSI0ICR
SSI Interrupt Clear
0x20
write-only
n
0x0
0x0
SSI_ICR_RORIC
SSI Receive Overrun Interrupt Clear
0
1
write-only
SSI_ICR_RTIC
SSI Receive Time-Out Interrupt Clear
1
2
write-only
SSI0IM
SSI Interrupt Mask
0x14
read-write
n
0x0
0x0
SSI_IM_RORIM
SSI Receive Overrun Interrupt Mask
0
1
SSI_IM_RTIM
SSI Receive Time-Out Interrupt Mask
1
2
SSI_IM_RXIM
SSI Receive FIFO Interrupt Mask
2
3
SSI_IM_TXIM
SSI Transmit FIFO Interrupt Mask
3
4
SSI0MIS
SSI Masked Interrupt Status
0x1C
read-write
n
0x0
0x0
SSI_MIS_RORMIS
SSI Receive Overrun Masked Interrupt Status
0
1
SSI_MIS_RTMIS
SSI Receive Time-Out Masked Interrupt Status
1
2
SSI_MIS_RXMIS
SSI Receive FIFO Masked Interrupt Status
2
3
SSI_MIS_TXMIS
SSI Transmit FIFO Masked Interrupt Status
3
4
SSI0RIS
SSI Raw Interrupt Status
0x18
read-write
n
0x0
0x0
SSI_RIS_RORRIS
SSI Receive Overrun Raw Interrupt Status
0
1
SSI_RIS_RTRIS
SSI Receive Time-Out Raw Interrupt Status
1
2
SSI_RIS_RXRIS
SSI Receive FIFO Raw Interrupt Status
2
3
SSI_RIS_TXRIS
SSI Transmit FIFO Raw Interrupt Status
3
4
SSI0SR
SSI Status
0xC
read-write
n
0x0
0x0
SSI_SR_BSY
SSI Busy Bit
4
5
SSI_SR_RFF
SSI Receive FIFO Full
3
4
SSI_SR_RNE
SSI Receive FIFO Not Empty
2
3
SSI_SR_TFE
SSI Transmit FIFO Empty
0
1
SSI_SR_TNF
SSI Transmit FIFO Not Full
1
2
SYSCTL
Register map for SYSCTL peripheral
SYSCTL
0x0
0x0
0x1000
registers
n
DC0
Device Capabilities 0
0x8
-1
read-write
n
0x0
0x0
SYSCTL_DC0_FLASHSZ
Flash Size
0
16
SYSCTL_DC0_FLASHSZ_128K
128 KB of Flash
0x3f
SYSCTL_DC0_SRAMSZ
SRAM Size
16
32
SYSCTL_DC0_SRAMSZ_32KB
32 KB of SRAM
0x7f
DC1
Device Capabilities 1
0x10
-1
read-write
n
0x0
0x0
SYSCTL_DC1_CAN0
CAN Module 0 Present
24
25
SYSCTL_DC1_JTAG
JTAG Present
0
1
SYSCTL_DC1_MINSYSDIV
System Clock Divider
12
16
SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x3
SYSCTL_DC1_MPU
MPU Present
7
8
SYSCTL_DC1_PLL
PLL Present
4
5
SYSCTL_DC1_SWD
SWD Present
1
2
SYSCTL_DC1_SWO
SWO Trace Port Present
2
3
SYSCTL_DC1_TEMP
Temp Sensor Present
5
6
SYSCTL_DC1_WDT0
Watchdog Timer 0 Present
3
4
DC2
Device Capabilities 2
0x14
-1
read-write
n
0x0
0x0
SYSCTL_DC2_COMP0
Analog Comparator 0 Present
24
25
SYSCTL_DC2_COMP1
Analog Comparator 1 Present
25
26
SYSCTL_DC2_COMP2
Analog Comparator 2 Present
26
27
SYSCTL_DC2_I2C0
I2C Module 0 Present
12
13
SYSCTL_DC2_SSI0
SSI Module 0 Present
4
5
SYSCTL_DC2_TIMER0
Timer Module 0 Present
16
17
SYSCTL_DC2_TIMER1
Timer Module 1 Present
17
18
SYSCTL_DC2_TIMER2
Timer Module 2 Present
18
19
SYSCTL_DC2_TIMER3
Timer Module 3 Present
19
20
SYSCTL_DC2_UART0
UART Module 0 Present
0
1
DC3
Device Capabilities 3
0x18
-1
read-write
n
0x0
0x0
SYSCTL_DC3_32KHZ
32KHz Input Clock Available
31
32
SYSCTL_DC3_C0MINUS
C0- Pin Present
6
7
SYSCTL_DC3_C0O
C0o Pin Present
8
9
SYSCTL_DC3_C0PLUS
C0+ Pin Present
7
8
SYSCTL_DC3_C1MINUS
C1- Pin Present
9
10
SYSCTL_DC3_C1O
C1o Pin Present
11
12
SYSCTL_DC3_C1PLUS
C1+ Pin Present
10
11
SYSCTL_DC3_C2MINUS
C2- Pin Present
12
13
SYSCTL_DC3_C2O
C2o Pin Present
14
15
SYSCTL_DC3_C2PLUS
C2+ Pin Present
13
14
SYSCTL_DC3_CCP0
CCP0 Pin Present
24
25
SYSCTL_DC3_CCP1
CCP1 Pin Present
25
26
SYSCTL_DC3_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC3_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC3_PWMFAULT
PWM Fault Pin Present
15
16
DC4
Device Capabilities 4
0x1C
-1
read-write
n
0x0
0x0
SYSCTL_DC4_GPIOA
GPIO Port A Present
0
1
SYSCTL_DC4_GPIOB
GPIO Port B Present
1
2
SYSCTL_DC4_GPIOC
GPIO Port C Present
2
3
SYSCTL_DC4_GPIOD
GPIO Port D Present
3
4
SYSCTL_DC4_GPIOE
GPIO Port E Present
4
5
SYSCTL_DC4_ROM
Internal Code ROM Present
12
13
SYSCTL_DC4_UDMA
Micro-DMA Module Present
13
14
DC5
Device Capabilities 5
0x20
-1
read-write
n
0x0
0x0
SYSCTL_DC5_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC5_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC5_PWMESYNC
PWM Extended SYNC Active
20
21
SYSCTL_DC5_PWMFAULT0
PWM Fault 0 Pin Present
24
25
DC6
Device Capabilities 6
0x24
-1
read-write
n
0x0
0x0
DC7
Device Capabilities 7
0x28
-1
read-write
n
0x0
0x0
SYSCTL_DC7_SSI0_RX
SSI0 RX on uDMA Ch10
10
11
SYSCTL_DC7_SSI0_TX
SSI0 TX on uDMA Ch11
11
12
SYSCTL_DC7_SW
Software transfer on uDMA Ch30
30
31
SYSCTL_DC7_UART0_RX
UART0 RX on uDMA Ch8
8
9
SYSCTL_DC7_UART0_TX
UART0 TX on uDMA Ch9
9
10
DCGC0
Deep Sleep Mode Clock Gating Control Register 0
0x120
-1
read-write
n
0x0
0x0
SYSCTL_DCGC0_CAN0
CAN0 Clock Gating Control
24
25
DCGC1
Deep-Sleep Mode Clock Gating Control Register 1
0x124
-1
read-write
n
0x0
0x0
SYSCTL_DCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_DCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_DCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_DCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_DCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_DCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_DCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_DCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_DCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_DCGC1_UART0
UART0 Clock Gating Control
0
1
DCGC2
Deep Sleep Mode Clock Gating Control Register 2
0x128
-1
read-write
n
0x0
0x0
SYSCTL_DCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_DCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_DCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_DCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_DCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_DCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
DID0
Device Identification 0
0x0
-1
read-write
n
0x0
0x0
SYSCTL_DID0_CLASS
Device Class
16
24
SYSCTL_DID0_CLASS_DUSTDEVIL
Stellaris(R) DustDevil-class devices
0x3
SYSCTL_DID0_MAJ
Major Revision
8
16
SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x0
SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x1
SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
0x2
SYSCTL_DID0_MIN
Minor Revision
0
8
SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x0
SYSCTL_DID0_MIN_1
First metal layer change
0x1
SYSCTL_DID0_MIN_2
Second metal layer change
0x2
SYSCTL_DID0_VER
DID0 Version
28
31
SYSCTL_DID0_VER_1
Second version of the DID0 register format
0x1
DID1
Device Identification 1
0x4
-1
read-write
n
0x0
0x0
SYSCTL_DID1_FAM
Family
24
28
SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
0x0
SYSCTL_DID1_PINCNT
Package Pin Count
13
16
SYSCTL_DID1_PINCNT_64
64-pin package
0x3
SYSCTL_DID1_PKG
Package Type
3
5
SYSCTL_DID1_PKG_SOIC
SOIC package
0x0
SYSCTL_DID1_PKG_QFP
LQFP package
0x1
SYSCTL_DID1_PKG_BGA
BGA package
0x2
SYSCTL_DID1_PRTNO
Part Number
16
24
SYSCTL_DID1_PRTNO_2671
LM3S2671
0x80
SYSCTL_DID1_QUAL
Qualification Status
0
2
SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x0
SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x1
SYSCTL_DID1_QUAL_FQ
Fully Qualified
0x2
SYSCTL_DID1_ROHS
RoHS-Compliance
2
3
SYSCTL_DID1_TEMP
Temperature Range
5
8
SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x0
SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x1
SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
0x2
SYSCTL_DID1_VER
DID1 Version
28
32
SYSCTL_DID1_VER_1
Second version of the DID1 register format
0x1
DSLPCLKCFG
Deep Sleep Clock Configuration
0x144
-1
read-write
n
0x0
0x0
SYSCTL_DSLPCLKCFG_D
Divider Field Override
23
29
SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x0
SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x1
SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x10
SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x11
SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x12
SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x13
SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x14
SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x15
SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x16
SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x17
SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x18
SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x19
SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1a
SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1b
SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1c
SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1d
SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1e
SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x1f
SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x2
SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x20
SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x21
SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x22
SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x23
SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x24
SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x25
SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x26
SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x27
SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x28
SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x29
SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2a
SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2b
SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2c
SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2d
SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2e
SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x2f
SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x3
SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x30
SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x31
SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x32
SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x33
SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x34
SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x35
SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x36
SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x37
SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x38
SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x39
SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3a
SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3b
SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3c
SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3d
SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3e
SYSCTL_DSLPCLKCFG_D_64
System clock /64
0x3f
SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x4
SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x5
SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x6
SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x7
SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x8
SYSCTL_DSLPCLKCFG_D_10
System clock /10
0x9
SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xa
SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xb
SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xc
SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xd
SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xe
SYSCTL_DSLPCLKCFG_D_16
System clock /16
0xf
SYSCTL_DSLPCLKCFG_O
Clock Source
4
7
SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x0
SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x1
SYSCTL_DSLPCLKCFG_O_30
30 kHz
0x3
GPIOHBCTL
GPIO High-Performance Bus Control
0x6C
-1
read-write
n
0x0
0x0
SYSCTL_GPIOHBCTL_PORTA
Port A Advanced High-Performance Bus
0
1
SYSCTL_GPIOHBCTL_PORTB
Port B Advanced High-Performance Bus
1
2
SYSCTL_GPIOHBCTL_PORTC
Port C Advanced High-Performance Bus
2
3
SYSCTL_GPIOHBCTL_PORTD
Port D Advanced High-Performance Bus
3
4
SYSCTL_GPIOHBCTL_PORTE
Port E Advanced High-Performance Bus
4
5
IMC
Interrupt Mask Control
0x54
-1
read-write
n
0x0
0x0
SYSCTL_IMC_BORIM
Brown-Out Reset Interrupt Mask
1
2
SYSCTL_IMC_MOSCPUPIM
MOSC Power Up Interrupt Mask
8
9
SYSCTL_IMC_PLLLIM
PLL Lock Interrupt Mask
6
7
LDOPCTL
LDO Power Control
0x34
-1
read-write
n
0x0
0x0
SYSCTL_LDOPCTL
LDO Output Voltage
0
6
SYSCTL_LDOPCTL_2_50V
2.50
0x0
SYSCTL_LDOPCTL_2_45V
2.45
0x1
SYSCTL_LDOPCTL_2_75V
2.75
0x1b
SYSCTL_LDOPCTL_2_70V
2.70
0x1c
SYSCTL_LDOPCTL_2_65V
2.65
0x1d
SYSCTL_LDOPCTL_2_60V
2.60
0x1e
SYSCTL_LDOPCTL_2_55V
2.55
0x1f
SYSCTL_LDOPCTL_2_40V
2.40
0x2
SYSCTL_LDOPCTL_2_35V
2.35
0x3
SYSCTL_LDOPCTL_2_30V
2.30
0x4
SYSCTL_LDOPCTL_2_25V
2.25
0x5
MISC
Masked Interrupt Status and Clear
0x58
-1
read-write
n
0x0
0x0
SYSCTL_MISC_BORMIS
BOR Masked Interrupt Status
1
2
SYSCTL_MISC_MOSCPUPMIS
MOSC Power Up Masked Interrupt Status
8
9
SYSCTL_MISC_PLLLMIS
PLL Lock Masked Interrupt Status
6
7
MOSCCTL
Main Oscillator Control
0x7C
-1
read-write
n
0x0
0x0
SYSCTL_MOSCCTL_CVAL
Clock Validation for MOSC
0
1
PBORCTL
Brown-Out Reset Control
0x30
-1
read-write
n
0x0
0x0
SYSCTL_PBORCTL_BORIOR
BOR Interrupt or Reset
1
2
PLLCFG
XTAL to PLL Translation
0x64
-1
read-write
n
0x0
0x0
SYSCTL_PLLCFG_F
PLL F Value
5
14
SYSCTL_PLLCFG_R
PLL R Value
0
5
RCC
Run-Mode Clock Configuration
0x60
-1
read-write
n
0x0
0x0
SYSCTL_RCC_ACG
Auto Clock Gating
27
28
SYSCTL_RCC_BYPASS
PLL Bypass
11
12
SYSCTL_RCC_IOSCDIS
Internal Oscillator Disable
1
2
SYSCTL_RCC_MOSCDIS
Main Oscillator Disable
0
1
SYSCTL_RCC_OSCSRC
Oscillator Source
4
6
SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x0
SYSCTL_RCC_OSCSRC_INT
IOSC
0x1
SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x2
SYSCTL_RCC_OSCSRC_30
30 kHz
0x3
SYSCTL_RCC_PWMDIV
PWM Unit Clock Divisor
17
20
SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x0
SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x1
SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x2
SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x3
SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x4
SYSCTL_RCC_PWMDIV_64
PWM clock /64
0x5
SYSCTL_RCC_PWRDN
PLL Power Down
13
14
SYSCTL_RCC_SYSDIV
System Clock Divisor
23
27
SYSCTL_RCC_SYSDIV_2
System clock /2
0x1
SYSCTL_RCC_SYSDIV_3
System clock /3
0x2
SYSCTL_RCC_SYSDIV_4
System clock /4
0x3
SYSCTL_RCC_SYSDIV_5
System clock /5
0x4
SYSCTL_RCC_SYSDIV_6
System clock /6
0x5
SYSCTL_RCC_SYSDIV_7
System clock /7
0x6
SYSCTL_RCC_SYSDIV_8
System clock /8
0x7
SYSCTL_RCC_SYSDIV_9
System clock /9
0x8
SYSCTL_RCC_SYSDIV_10
System clock /10
0x9
SYSCTL_RCC_SYSDIV_11
System clock /11
0xa
SYSCTL_RCC_SYSDIV_12
System clock /12
0xb
SYSCTL_RCC_SYSDIV_13
System clock /13
0xc
SYSCTL_RCC_SYSDIV_14
System clock /14
0xd
SYSCTL_RCC_SYSDIV_15
System clock /15
0xe
SYSCTL_RCC_SYSDIV_16
System clock /16
0xf
SYSCTL_RCC_USEPWMDIV
Enable PWM Clock Divisor
20
21
SYSCTL_RCC_USESYSDIV
Enable System Clock Divider
22
23
SYSCTL_RCC_XTAL
Crystal Value
6
11
SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x0
SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x1
SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x10
SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x11
SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x12
SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x13
SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x14
SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x15
SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
0x16
SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x2
SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x3
SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x4
SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x5
SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x6
SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x7
SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x8
SYSCTL_RCC_XTAL_5MHZ
5 MHz
0x9
SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xa
SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xb
SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xc
SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xd
SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xe
SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0xf
RCC2
Run-Mode Clock Configuration 2
0x70
-1
read-write
n
0x0
0x0
SYSCTL_RCC2_BYPASS2
PLL Bypass 2
11
12
SYSCTL_RCC2_OSCSRC2
Oscillator Source 2
4
7
SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x0
SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x1
SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x2
SYSCTL_RCC2_OSCSRC2_30
30 kHz
0x3
SYSCTL_RCC2_PWRDN2
Power-Down PLL 2
13
14
SYSCTL_RCC2_SYSDIV2
System Clock Divisor 2
23
29
SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x1
SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x10
SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x11
SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x12
SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x13
SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x14
SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x15
SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x16
SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x17
SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x18
SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x19
SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1a
SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1b
SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1c
SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1d
SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1e
SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x1f
SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x2
SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x20
SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x21
SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x22
SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x23
SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x24
SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x25
SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x26
SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x27
SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x28
SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x29
SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2a
SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2b
SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2c
SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2d
SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2e
SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x2f
SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x3
SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x30
SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x31
SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x32
SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x33
SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x34
SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x35
SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x36
SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x37
SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x38
SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x39
SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3a
SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3b
SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3c
SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3d
SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3e
SYSCTL_RCC2_SYSDIV2_64
System clock /64
0x3f
SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x4
SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x5
SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x6
SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x7
SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x8
SYSCTL_RCC2_SYSDIV2_10
System clock /10
0x9
SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xa
SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xb
SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xc
SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xd
SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xe
SYSCTL_RCC2_SYSDIV2_16
System clock /16
0xf
SYSCTL_RCC2_USERCC2
Use RCC2
31
32
RCGC0
Run Mode Clock Gating Control Register 0
0x100
-1
read-write
n
0x0
0x0
SYSCTL_RCGC0_ADCSPD
ADC Sample Speed
8
10
SYSCTL_RCGC0_ADCSPD125K
125K samples/second
0x0
SYSCTL_RCGC0_ADCSPD250K
250K samples/second
0x1
SYSCTL_RCGC0_ADCSPD500K
500K samples/second
0x2
SYSCTL_RCGC0_CAN0
CAN0 Clock Gating Control
24
25
RCGC1
Run Mode Clock Gating Control Register 1
0x104
-1
read-write
n
0x0
0x0
SYSCTL_RCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_RCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_RCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_RCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_RCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_RCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_RCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_RCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_RCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_RCGC1_UART0
UART0 Clock Gating Control
0
1
RCGC2
Run Mode Clock Gating Control Register 2
0x108
-1
read-write
n
0x0
0x0
SYSCTL_RCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_RCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_RCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_RCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_RCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_RCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
RESC
Reset Cause
0x5C
-1
read-write
n
0x0
0x0
SYSCTL_RESC_BOR
Brown-Out Reset
2
3
SYSCTL_RESC_EXT
External Reset
0
1
SYSCTL_RESC_MOSCFAIL
MOSC Failure Reset
16
17
SYSCTL_RESC_POR
Power-On Reset
1
2
SYSCTL_RESC_SW
Software Reset
4
5
RIS
Raw Interrupt Status
0x50
-1
read-write
n
0x0
0x0
SYSCTL_RIS_BORRIS
Brown-Out Reset Raw Interrupt Status
1
2
SYSCTL_RIS_MOSCPUPRIS
MOSC Power Up Raw Interrupt Status
8
9
SYSCTL_RIS_PLLLRIS
PLL Lock Raw Interrupt Status
6
7
SCGC0
Sleep Mode Clock Gating Control Register 0
0x110
-1
read-write
n
0x0
0x0
SYSCTL_SCGC0_ADCSPD
ADC Sample Speed
8
10
SYSCTL_SCGC0_ADCSPD125K
125K samples/second
0x0
SYSCTL_SCGC0_ADCSPD250K
250K samples/second
0x1
SYSCTL_SCGC0_ADCSPD500K
500K samples/second
0x2
SYSCTL_SCGC0_CAN0
CAN0 Clock Gating Control
24
25
SCGC1
Sleep Mode Clock Gating Control Register 1
0x114
-1
read-write
n
0x0
0x0
SYSCTL_SCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_SCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_SCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_SCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_SCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_SCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_SCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_SCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_SCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_SCGC1_UART0
UART0 Clock Gating Control
0
1
SCGC2
Sleep Mode Clock Gating Control Register 2
0x118
-1
read-write
n
0x0
0x0
SYSCTL_SCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_SCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_SCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_SCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_SCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_SCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SRCR0
Software Reset Control 0
0x40
-1
read-write
n
0x0
0x0
SYSCTL_SRCR0_CAN0
CAN0 Reset Control
24
25
SRCR1
Software Reset Control 1
0x44
-1
read-write
n
0x0
0x0
SYSCTL_SRCR1_COMP0
Analog Comp 0 Reset Control
24
25
SYSCTL_SRCR1_COMP1
Analog Comp 1 Reset Control
25
26
SYSCTL_SRCR1_COMP2
Analog Comp 2 Reset Control
26
27
SYSCTL_SRCR1_I2C0
I2C0 Reset Control
12
13
SYSCTL_SRCR1_SSI0
SSI0 Reset Control
4
5
SYSCTL_SRCR1_TIMER0
Timer 0 Reset Control
16
17
SYSCTL_SRCR1_TIMER1
Timer 1 Reset Control
17
18
SYSCTL_SRCR1_TIMER2
Timer 2 Reset Control
18
19
SYSCTL_SRCR1_TIMER3
Timer 3 Reset Control
19
20
SYSCTL_SRCR1_UART0
UART0 Reset Control
0
1
SRCR2
Software Reset Control 2
0x48
-1
read-write
n
0x0
0x0
SYSCTL_SRCR2_GPIOA
Port A Reset Control
0
1
SYSCTL_SRCR2_GPIOB
Port B Reset Control
1
2
SYSCTL_SRCR2_GPIOC
Port C Reset Control
2
3
SYSCTL_SRCR2_GPIOD
Port D Reset Control
3
4
SYSCTL_SRCR2_GPIOE
Port E Reset Control
4
5
SYSCTL_SRCR2_UDMA
Micro-DMA Reset Control
13
14
SYSCTLDC0
Device Capabilities 0
0x8
read-write
n
0x0
0x0
SYSCTL_DC0_FLASHSZ
Flash Size
0
16
SYSCTL_DC0_FLASHSZ_128K
128 KB of Flash
0x3f
SYSCTL_DC0_SRAMSZ
SRAM Size
16
32
SYSCTL_DC0_SRAMSZ_32KB
32 KB of SRAM
0x7f
SYSCTLDC1
Device Capabilities 1
0x10
read-write
n
0x0
0x0
SYSCTL_DC1_CAN0
CAN Module 0 Present
24
25
SYSCTL_DC1_JTAG
JTAG Present
0
1
SYSCTL_DC1_MINSYSDIV
System Clock Divider
12
16
SYSCTL_DC1_MINSYSDIV_50
Specifies a 50-MHz CPU clock with a PLL divider of 4
0x3
SYSCTL_DC1_MPU
MPU Present
7
8
SYSCTL_DC1_PLL
PLL Present
4
5
SYSCTL_DC1_SWD
SWD Present
1
2
SYSCTL_DC1_SWO
SWO Trace Port Present
2
3
SYSCTL_DC1_TEMP
Temp Sensor Present
5
6
SYSCTL_DC1_WDT0
Watchdog Timer 0 Present
3
4
SYSCTLDC2
Device Capabilities 2
0x14
read-write
n
0x0
0x0
SYSCTL_DC2_COMP0
Analog Comparator 0 Present
24
25
SYSCTL_DC2_COMP1
Analog Comparator 1 Present
25
26
SYSCTL_DC2_COMP2
Analog Comparator 2 Present
26
27
SYSCTL_DC2_I2C0
I2C Module 0 Present
12
13
SYSCTL_DC2_SSI0
SSI Module 0 Present
4
5
SYSCTL_DC2_TIMER0
Timer Module 0 Present
16
17
SYSCTL_DC2_TIMER1
Timer Module 1 Present
17
18
SYSCTL_DC2_TIMER2
Timer Module 2 Present
18
19
SYSCTL_DC2_TIMER3
Timer Module 3 Present
19
20
SYSCTL_DC2_UART0
UART Module 0 Present
0
1
SYSCTLDC3
Device Capabilities 3
0x18
read-write
n
0x0
0x0
SYSCTL_DC3_32KHZ
32KHz Input Clock Available
31
32
SYSCTL_DC3_C0MINUS
C0- Pin Present
6
7
SYSCTL_DC3_C0O
C0o Pin Present
8
9
SYSCTL_DC3_C0PLUS
C0+ Pin Present
7
8
SYSCTL_DC3_C1MINUS
C1- Pin Present
9
10
SYSCTL_DC3_C1O
C1o Pin Present
11
12
SYSCTL_DC3_C1PLUS
C1+ Pin Present
10
11
SYSCTL_DC3_C2MINUS
C2- Pin Present
12
13
SYSCTL_DC3_C2O
C2o Pin Present
14
15
SYSCTL_DC3_C2PLUS
C2+ Pin Present
13
14
SYSCTL_DC3_CCP0
CCP0 Pin Present
24
25
SYSCTL_DC3_CCP1
CCP1 Pin Present
25
26
SYSCTL_DC3_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC3_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC3_PWMFAULT
PWM Fault Pin Present
15
16
SYSCTLDC4
Device Capabilities 4
0x1C
read-write
n
0x0
0x0
SYSCTL_DC4_GPIOA
GPIO Port A Present
0
1
SYSCTL_DC4_GPIOB
GPIO Port B Present
1
2
SYSCTL_DC4_GPIOC
GPIO Port C Present
2
3
SYSCTL_DC4_GPIOD
GPIO Port D Present
3
4
SYSCTL_DC4_GPIOE
GPIO Port E Present
4
5
SYSCTL_DC4_ROM
Internal Code ROM Present
12
13
SYSCTL_DC4_UDMA
Micro-DMA Module Present
13
14
SYSCTLDC5
Device Capabilities 5
0x20
read-write
n
0x0
0x0
SYSCTL_DC5_PWM0
PWM0 Pin Present
0
1
SYSCTL_DC5_PWM1
PWM1 Pin Present
1
2
SYSCTL_DC5_PWMESYNC
PWM Extended SYNC Active
20
21
SYSCTL_DC5_PWMFAULT0
PWM Fault 0 Pin Present
24
25
SYSCTLDC6
Device Capabilities 6
0x24
read-write
n
0x0
0x0
SYSCTLDC7
Device Capabilities 7
0x28
read-write
n
0x0
0x0
SYSCTL_DC7_SSI0_RX
SSI0 RX on uDMA Ch10
10
11
SYSCTL_DC7_SSI0_TX
SSI0 TX on uDMA Ch11
11
12
SYSCTL_DC7_SW
Software transfer on uDMA Ch30
30
31
SYSCTL_DC7_UART0_RX
UART0 RX on uDMA Ch8
8
9
SYSCTL_DC7_UART0_TX
UART0 TX on uDMA Ch9
9
10
SYSCTLDCGC0
Deep Sleep Mode Clock Gating Control Register 0
0x120
read-write
n
0x0
0x0
SYSCTL_DCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTLDCGC1
Deep-Sleep Mode Clock Gating Control Register 1
0x124
read-write
n
0x0
0x0
SYSCTL_DCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_DCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_DCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_DCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_DCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_DCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_DCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_DCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_DCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_DCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTLDCGC2
Deep Sleep Mode Clock Gating Control Register 2
0x128
read-write
n
0x0
0x0
SYSCTL_DCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_DCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_DCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_DCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_DCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_DCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTLDID0
Device Identification 0
0x0
read-write
n
0x0
0x0
SYSCTL_DID0_CLASS
Device Class
16
24
SYSCTL_DID0_CLASS_DUSTDEVIL
Stellaris(R) DustDevil-class devices
0x3
SYSCTL_DID0_MAJ
Major Revision
8
16
SYSCTL_DID0_MAJ_REVA
Revision A (initial device)
0x0
SYSCTL_DID0_MAJ_REVB
Revision B (first base layer revision)
0x1
SYSCTL_DID0_MAJ_REVC
Revision C (second base layer revision)
0x2
SYSCTL_DID0_MIN
Minor Revision
0
8
SYSCTL_DID0_MIN_0
Initial device, or a major revision update
0x0
SYSCTL_DID0_MIN_1
First metal layer change
0x1
SYSCTL_DID0_MIN_2
Second metal layer change
0x2
SYSCTL_DID0_VER
DID0 Version
28
31
SYSCTL_DID0_VER_1
Second version of the DID0 register format
0x1
SYSCTLDID1
Device Identification 1
0x4
read-write
n
0x0
0x0
SYSCTL_DID1_FAM
Family
24
28
SYSCTL_DID1_FAM_STELLARIS
Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S
0x0
SYSCTL_DID1_PINCNT
Package Pin Count
13
16
SYSCTL_DID1_PINCNT_64
64-pin package
0x3
SYSCTL_DID1_PKG
Package Type
3
5
SYSCTL_DID1_PKG_SOIC
SOIC package
0x0
SYSCTL_DID1_PKG_QFP
LQFP package
0x1
SYSCTL_DID1_PKG_BGA
BGA package
0x2
SYSCTL_DID1_PRTNO
Part Number
16
24
SYSCTL_DID1_PRTNO_2671
LM3S2671
0x80
SYSCTL_DID1_QUAL
Qualification Status
0
2
SYSCTL_DID1_QUAL_ES
Engineering Sample (unqualified)
0x0
SYSCTL_DID1_QUAL_PP
Pilot Production (unqualified)
0x1
SYSCTL_DID1_QUAL_FQ
Fully Qualified
0x2
SYSCTL_DID1_ROHS
RoHS-Compliance
2
3
SYSCTL_DID1_TEMP
Temperature Range
5
8
SYSCTL_DID1_TEMP_C
Commercial temperature range (0C to 70C)
0x0
SYSCTL_DID1_TEMP_I
Industrial temperature range (-40C to 85C)
0x1
SYSCTL_DID1_TEMP_E
Extended temperature range (-40C to 105C)
0x2
SYSCTL_DID1_VER
DID1 Version
28
32
SYSCTL_DID1_VER_1
Second version of the DID1 register format
0x1
SYSCTLDSLPCLKCFG
Deep Sleep Clock Configuration
0x144
read-write
n
0x0
0x0
SYSCTL_DSLPCLKCFG_D
Divider Field Override
23
29
SYSCTL_DSLPCLKCFG_D_1
System clock /1
0x0
SYSCTL_DSLPCLKCFG_D_2
System clock /2
0x1
SYSCTL_DSLPCLKCFG_D_17
System clock /17
0x10
SYSCTL_DSLPCLKCFG_D_18
System clock /18
0x11
SYSCTL_DSLPCLKCFG_D_19
System clock /19
0x12
SYSCTL_DSLPCLKCFG_D_20
System clock /20
0x13
SYSCTL_DSLPCLKCFG_D_21
System clock /21
0x14
SYSCTL_DSLPCLKCFG_D_22
System clock /22
0x15
SYSCTL_DSLPCLKCFG_D_23
System clock /23
0x16
SYSCTL_DSLPCLKCFG_D_24
System clock /24
0x17
SYSCTL_DSLPCLKCFG_D_25
System clock /25
0x18
SYSCTL_DSLPCLKCFG_D_26
System clock /26
0x19
SYSCTL_DSLPCLKCFG_D_27
System clock /27
0x1a
SYSCTL_DSLPCLKCFG_D_28
System clock /28
0x1b
SYSCTL_DSLPCLKCFG_D_29
System clock /29
0x1c
SYSCTL_DSLPCLKCFG_D_30
System clock /30
0x1d
SYSCTL_DSLPCLKCFG_D_31
System clock /31
0x1e
SYSCTL_DSLPCLKCFG_D_32
System clock /32
0x1f
SYSCTL_DSLPCLKCFG_D_3
System clock /3
0x2
SYSCTL_DSLPCLKCFG_D_33
System clock /33
0x20
SYSCTL_DSLPCLKCFG_D_34
System clock /34
0x21
SYSCTL_DSLPCLKCFG_D_35
System clock /35
0x22
SYSCTL_DSLPCLKCFG_D_36
System clock /36
0x23
SYSCTL_DSLPCLKCFG_D_37
System clock /37
0x24
SYSCTL_DSLPCLKCFG_D_38
System clock /38
0x25
SYSCTL_DSLPCLKCFG_D_39
System clock /39
0x26
SYSCTL_DSLPCLKCFG_D_40
System clock /40
0x27
SYSCTL_DSLPCLKCFG_D_41
System clock /41
0x28
SYSCTL_DSLPCLKCFG_D_42
System clock /42
0x29
SYSCTL_DSLPCLKCFG_D_43
System clock /43
0x2a
SYSCTL_DSLPCLKCFG_D_44
System clock /44
0x2b
SYSCTL_DSLPCLKCFG_D_45
System clock /45
0x2c
SYSCTL_DSLPCLKCFG_D_46
System clock /46
0x2d
SYSCTL_DSLPCLKCFG_D_47
System clock /47
0x2e
SYSCTL_DSLPCLKCFG_D_48
System clock /48
0x2f
SYSCTL_DSLPCLKCFG_D_4
System clock /4
0x3
SYSCTL_DSLPCLKCFG_D_49
System clock /49
0x30
SYSCTL_DSLPCLKCFG_D_50
System clock /50
0x31
SYSCTL_DSLPCLKCFG_D_51
System clock /51
0x32
SYSCTL_DSLPCLKCFG_D_52
System clock /52
0x33
SYSCTL_DSLPCLKCFG_D_53
System clock /53
0x34
SYSCTL_DSLPCLKCFG_D_54
System clock /54
0x35
SYSCTL_DSLPCLKCFG_D_55
System clock /55
0x36
SYSCTL_DSLPCLKCFG_D_56
System clock /56
0x37
SYSCTL_DSLPCLKCFG_D_57
System clock /57
0x38
SYSCTL_DSLPCLKCFG_D_58
System clock /58
0x39
SYSCTL_DSLPCLKCFG_D_59
System clock /59
0x3a
SYSCTL_DSLPCLKCFG_D_60
System clock /60
0x3b
SYSCTL_DSLPCLKCFG_D_61
System clock /61
0x3c
SYSCTL_DSLPCLKCFG_D_62
System clock /62
0x3d
SYSCTL_DSLPCLKCFG_D_63
System clock /63
0x3e
SYSCTL_DSLPCLKCFG_D_64
System clock /64
0x3f
SYSCTL_DSLPCLKCFG_D_5
System clock /5
0x4
SYSCTL_DSLPCLKCFG_D_6
System clock /6
0x5
SYSCTL_DSLPCLKCFG_D_7
System clock /7
0x6
SYSCTL_DSLPCLKCFG_D_8
System clock /8
0x7
SYSCTL_DSLPCLKCFG_D_9
System clock /9
0x8
SYSCTL_DSLPCLKCFG_D_10
System clock /10
0x9
SYSCTL_DSLPCLKCFG_D_11
System clock /11
0xa
SYSCTL_DSLPCLKCFG_D_12
System clock /12
0xb
SYSCTL_DSLPCLKCFG_D_13
System clock /13
0xc
SYSCTL_DSLPCLKCFG_D_14
System clock /14
0xd
SYSCTL_DSLPCLKCFG_D_15
System clock /15
0xe
SYSCTL_DSLPCLKCFG_D_16
System clock /16
0xf
SYSCTL_DSLPCLKCFG_O
Clock Source
4
7
SYSCTL_DSLPCLKCFG_O_IGN
MOSC
0x0
SYSCTL_DSLPCLKCFG_O_IO
PIOSC
0x1
SYSCTL_DSLPCLKCFG_O_30
30 kHz
0x3
SYSCTLGPIOHBCTL
GPIO High-Performance Bus Control
0x6C
read-write
n
0x0
0x0
SYSCTL_GPIOHBCTL_PORTA
Port A Advanced High-Performance Bus
0
1
SYSCTL_GPIOHBCTL_PORTB
Port B Advanced High-Performance Bus
1
2
SYSCTL_GPIOHBCTL_PORTC
Port C Advanced High-Performance Bus
2
3
SYSCTL_GPIOHBCTL_PORTD
Port D Advanced High-Performance Bus
3
4
SYSCTL_GPIOHBCTL_PORTE
Port E Advanced High-Performance Bus
4
5
SYSCTLIMC
Interrupt Mask Control
0x54
read-write
n
0x0
0x0
SYSCTL_IMC_BORIM
Brown-Out Reset Interrupt Mask
1
2
SYSCTL_IMC_MOSCPUPIM
MOSC Power Up Interrupt Mask
8
9
SYSCTL_IMC_PLLLIM
PLL Lock Interrupt Mask
6
7
SYSCTLLDOPCTL
LDO Power Control
0x34
read-write
n
0x0
0x0
SYSCTL_LDOPCTL
LDO Output Voltage
0
6
SYSCTL_LDOPCTL_2_50V
2.50
0x0
SYSCTL_LDOPCTL_2_45V
2.45
0x1
SYSCTL_LDOPCTL_2_75V
2.75
0x1b
SYSCTL_LDOPCTL_2_70V
2.70
0x1c
SYSCTL_LDOPCTL_2_65V
2.65
0x1d
SYSCTL_LDOPCTL_2_60V
2.60
0x1e
SYSCTL_LDOPCTL_2_55V
2.55
0x1f
SYSCTL_LDOPCTL_2_40V
2.40
0x2
SYSCTL_LDOPCTL_2_35V
2.35
0x3
SYSCTL_LDOPCTL_2_30V
2.30
0x4
SYSCTL_LDOPCTL_2_25V
2.25
0x5
SYSCTLMISC
Masked Interrupt Status and Clear
0x58
read-write
n
0x0
0x0
SYSCTL_MISC_BORMIS
BOR Masked Interrupt Status
1
2
SYSCTL_MISC_MOSCPUPMIS
MOSC Power Up Masked Interrupt Status
8
9
SYSCTL_MISC_PLLLMIS
PLL Lock Masked Interrupt Status
6
7
SYSCTLMOSCCTL
Main Oscillator Control
0x7C
read-write
n
0x0
0x0
SYSCTL_MOSCCTL_CVAL
Clock Validation for MOSC
0
1
SYSCTLPBORCTL
Brown-Out Reset Control
0x30
read-write
n
0x0
0x0
SYSCTL_PBORCTL_BORIOR
BOR Interrupt or Reset
1
2
SYSCTLPLLCFG
XTAL to PLL Translation
0x64
read-write
n
0x0
0x0
SYSCTL_PLLCFG_F
PLL F Value
5
14
SYSCTL_PLLCFG_R
PLL R Value
0
5
SYSCTLRCC
Run-Mode Clock Configuration
0x60
read-write
n
0x0
0x0
SYSCTL_RCC_ACG
Auto Clock Gating
27
28
SYSCTL_RCC_BYPASS
PLL Bypass
11
12
SYSCTL_RCC_IOSCDIS
Internal Oscillator Disable
1
2
SYSCTL_RCC_MOSCDIS
Main Oscillator Disable
0
1
SYSCTL_RCC_OSCSRC
Oscillator Source
4
6
SYSCTL_RCC_OSCSRC_MAIN
MOSC
0x0
SYSCTL_RCC_OSCSRC_INT
IOSC
0x1
SYSCTL_RCC_OSCSRC_INT4
IOSC/4
0x2
SYSCTL_RCC_OSCSRC_30
30 kHz
0x3
SYSCTL_RCC_PWMDIV
PWM Unit Clock Divisor
17
20
SYSCTL_RCC_PWMDIV_2
PWM clock /2
0x0
SYSCTL_RCC_PWMDIV_4
PWM clock /4
0x1
SYSCTL_RCC_PWMDIV_8
PWM clock /8
0x2
SYSCTL_RCC_PWMDIV_16
PWM clock /16
0x3
SYSCTL_RCC_PWMDIV_32
PWM clock /32
0x4
SYSCTL_RCC_PWMDIV_64
PWM clock /64
0x5
SYSCTL_RCC_PWRDN
PLL Power Down
13
14
SYSCTL_RCC_SYSDIV
System Clock Divisor
23
27
SYSCTL_RCC_SYSDIV_2
System clock /2
0x1
SYSCTL_RCC_SYSDIV_3
System clock /3
0x2
SYSCTL_RCC_SYSDIV_4
System clock /4
0x3
SYSCTL_RCC_SYSDIV_5
System clock /5
0x4
SYSCTL_RCC_SYSDIV_6
System clock /6
0x5
SYSCTL_RCC_SYSDIV_7
System clock /7
0x6
SYSCTL_RCC_SYSDIV_8
System clock /8
0x7
SYSCTL_RCC_SYSDIV_9
System clock /9
0x8
SYSCTL_RCC_SYSDIV_10
System clock /10
0x9
SYSCTL_RCC_SYSDIV_11
System clock /11
0xa
SYSCTL_RCC_SYSDIV_12
System clock /12
0xb
SYSCTL_RCC_SYSDIV_13
System clock /13
0xc
SYSCTL_RCC_SYSDIV_14
System clock /14
0xd
SYSCTL_RCC_SYSDIV_15
System clock /15
0xe
SYSCTL_RCC_SYSDIV_16
System clock /16
0xf
SYSCTL_RCC_USEPWMDIV
Enable PWM Clock Divisor
20
21
SYSCTL_RCC_USESYSDIV
Enable System Clock Divider
22
23
SYSCTL_RCC_XTAL
Crystal Value
6
11
SYSCTL_RCC_XTAL_1MHZ
1 MHz
0x0
SYSCTL_RCC_XTAL_1_84MHZ
1.8432 MHz
0x1
SYSCTL_RCC_XTAL_10MHZ
10 MHz
0x10
SYSCTL_RCC_XTAL_12MHZ
12 MHz
0x11
SYSCTL_RCC_XTAL_12_2MHZ
12.288 MHz
0x12
SYSCTL_RCC_XTAL_13_5MHZ
13.56 MHz
0x13
SYSCTL_RCC_XTAL_14_3MHZ
14.31818 MHz
0x14
SYSCTL_RCC_XTAL_16MHZ
16 MHz
0x15
SYSCTL_RCC_XTAL_16_3MHZ
16.384 MHz
0x16
SYSCTL_RCC_XTAL_2MHZ
2 MHz
0x2
SYSCTL_RCC_XTAL_2_45MHZ
2.4576 MHz
0x3
SYSCTL_RCC_XTAL_3_57MHZ
3.579545 MHz
0x4
SYSCTL_RCC_XTAL_3_68MHZ
3.6864 MHz
0x5
SYSCTL_RCC_XTAL_4MHZ
4 MHz
0x6
SYSCTL_RCC_XTAL_4_09MHZ
4.096 MHz
0x7
SYSCTL_RCC_XTAL_4_91MHZ
4.9152 MHz
0x8
SYSCTL_RCC_XTAL_5MHZ
5 MHz
0x9
SYSCTL_RCC_XTAL_5_12MHZ
5.12 MHz
0xa
SYSCTL_RCC_XTAL_6MHZ
6 MHz
0xb
SYSCTL_RCC_XTAL_6_14MHZ
6.144 MHz
0xc
SYSCTL_RCC_XTAL_7_37MHZ
7.3728 MHz
0xd
SYSCTL_RCC_XTAL_8MHZ
8 MHz
0xe
SYSCTL_RCC_XTAL_8_19MHZ
8.192 MHz
0xf
SYSCTLRCC2
Run-Mode Clock Configuration 2
0x70
read-write
n
0x0
0x0
SYSCTL_RCC2_BYPASS2
PLL Bypass 2
11
12
SYSCTL_RCC2_OSCSRC2
Oscillator Source 2
4
7
SYSCTL_RCC2_OSCSRC2_MO
MOSC
0x0
SYSCTL_RCC2_OSCSRC2_IO
PIOSC
0x1
SYSCTL_RCC2_OSCSRC2_IO4
PIOSC/4
0x2
SYSCTL_RCC2_OSCSRC2_30
30 kHz
0x3
SYSCTL_RCC2_PWRDN2
Power-Down PLL 2
13
14
SYSCTL_RCC2_SYSDIV2
System Clock Divisor 2
23
29
SYSCTL_RCC2_SYSDIV2_2
System clock /2
0x1
SYSCTL_RCC2_SYSDIV2_17
System clock /17
0x10
SYSCTL_RCC2_SYSDIV2_18
System clock /18
0x11
SYSCTL_RCC2_SYSDIV2_19
System clock /19
0x12
SYSCTL_RCC2_SYSDIV2_20
System clock /20
0x13
SYSCTL_RCC2_SYSDIV2_21
System clock /21
0x14
SYSCTL_RCC2_SYSDIV2_22
System clock /22
0x15
SYSCTL_RCC2_SYSDIV2_23
System clock /23
0x16
SYSCTL_RCC2_SYSDIV2_24
System clock /24
0x17
SYSCTL_RCC2_SYSDIV2_25
System clock /25
0x18
SYSCTL_RCC2_SYSDIV2_26
System clock /26
0x19
SYSCTL_RCC2_SYSDIV2_27
System clock /27
0x1a
SYSCTL_RCC2_SYSDIV2_28
System clock /28
0x1b
SYSCTL_RCC2_SYSDIV2_29
System clock /29
0x1c
SYSCTL_RCC2_SYSDIV2_30
System clock /30
0x1d
SYSCTL_RCC2_SYSDIV2_31
System clock /31
0x1e
SYSCTL_RCC2_SYSDIV2_32
System clock /32
0x1f
SYSCTL_RCC2_SYSDIV2_3
System clock /3
0x2
SYSCTL_RCC2_SYSDIV2_33
System clock /33
0x20
SYSCTL_RCC2_SYSDIV2_34
System clock /34
0x21
SYSCTL_RCC2_SYSDIV2_35
System clock /35
0x22
SYSCTL_RCC2_SYSDIV2_36
System clock /36
0x23
SYSCTL_RCC2_SYSDIV2_37
System clock /37
0x24
SYSCTL_RCC2_SYSDIV2_38
System clock /38
0x25
SYSCTL_RCC2_SYSDIV2_39
System clock /39
0x26
SYSCTL_RCC2_SYSDIV2_40
System clock /40
0x27
SYSCTL_RCC2_SYSDIV2_41
System clock /41
0x28
SYSCTL_RCC2_SYSDIV2_42
System clock /42
0x29
SYSCTL_RCC2_SYSDIV2_43
System clock /43
0x2a
SYSCTL_RCC2_SYSDIV2_44
System clock /44
0x2b
SYSCTL_RCC2_SYSDIV2_45
System clock /45
0x2c
SYSCTL_RCC2_SYSDIV2_46
System clock /46
0x2d
SYSCTL_RCC2_SYSDIV2_47
System clock /47
0x2e
SYSCTL_RCC2_SYSDIV2_48
System clock /48
0x2f
SYSCTL_RCC2_SYSDIV2_4
System clock /4
0x3
SYSCTL_RCC2_SYSDIV2_49
System clock /49
0x30
SYSCTL_RCC2_SYSDIV2_50
System clock /50
0x31
SYSCTL_RCC2_SYSDIV2_51
System clock /51
0x32
SYSCTL_RCC2_SYSDIV2_52
System clock /52
0x33
SYSCTL_RCC2_SYSDIV2_53
System clock /53
0x34
SYSCTL_RCC2_SYSDIV2_54
System clock /54
0x35
SYSCTL_RCC2_SYSDIV2_55
System clock /55
0x36
SYSCTL_RCC2_SYSDIV2_56
System clock /56
0x37
SYSCTL_RCC2_SYSDIV2_57
System clock /57
0x38
SYSCTL_RCC2_SYSDIV2_58
System clock /58
0x39
SYSCTL_RCC2_SYSDIV2_59
System clock /59
0x3a
SYSCTL_RCC2_SYSDIV2_60
System clock /60
0x3b
SYSCTL_RCC2_SYSDIV2_61
System clock /61
0x3c
SYSCTL_RCC2_SYSDIV2_62
System clock /62
0x3d
SYSCTL_RCC2_SYSDIV2_63
System clock /63
0x3e
SYSCTL_RCC2_SYSDIV2_64
System clock /64
0x3f
SYSCTL_RCC2_SYSDIV2_5
System clock /5
0x4
SYSCTL_RCC2_SYSDIV2_6
System clock /6
0x5
SYSCTL_RCC2_SYSDIV2_7
System clock /7
0x6
SYSCTL_RCC2_SYSDIV2_8
System clock /8
0x7
SYSCTL_RCC2_SYSDIV2_9
System clock /9
0x8
SYSCTL_RCC2_SYSDIV2_10
System clock /10
0x9
SYSCTL_RCC2_SYSDIV2_11
System clock /11
0xa
SYSCTL_RCC2_SYSDIV2_12
System clock /12
0xb
SYSCTL_RCC2_SYSDIV2_13
System clock /13
0xc
SYSCTL_RCC2_SYSDIV2_14
System clock /14
0xd
SYSCTL_RCC2_SYSDIV2_15
System clock /15
0xe
SYSCTL_RCC2_SYSDIV2_16
System clock /16
0xf
SYSCTL_RCC2_USERCC2
Use RCC2
31
32
SYSCTLRCGC0
Run Mode Clock Gating Control Register 0
0x100
read-write
n
0x0
0x0
SYSCTL_RCGC0_ADCSPD
ADC Sample Speed
8
10
SYSCTL_RCGC0_ADCSPD125K
125K samples/second
0x0
SYSCTL_RCGC0_ADCSPD250K
250K samples/second
0x1
SYSCTL_RCGC0_ADCSPD500K
500K samples/second
0x2
SYSCTL_RCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTLRCGC1
Run Mode Clock Gating Control Register 1
0x104
read-write
n
0x0
0x0
SYSCTL_RCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_RCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_RCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_RCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_RCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_RCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_RCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_RCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_RCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_RCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTLRCGC2
Run Mode Clock Gating Control Register 2
0x108
read-write
n
0x0
0x0
SYSCTL_RCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_RCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_RCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_RCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_RCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_RCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTLRESC
Reset Cause
0x5C
read-write
n
0x0
0x0
SYSCTL_RESC_BOR
Brown-Out Reset
2
3
SYSCTL_RESC_EXT
External Reset
0
1
SYSCTL_RESC_MOSCFAIL
MOSC Failure Reset
16
17
SYSCTL_RESC_POR
Power-On Reset
1
2
SYSCTL_RESC_SW
Software Reset
4
5
SYSCTLRIS
Raw Interrupt Status
0x50
read-write
n
0x0
0x0
SYSCTL_RIS_BORRIS
Brown-Out Reset Raw Interrupt Status
1
2
SYSCTL_RIS_MOSCPUPRIS
MOSC Power Up Raw Interrupt Status
8
9
SYSCTL_RIS_PLLLRIS
PLL Lock Raw Interrupt Status
6
7
SYSCTLSCGC0
Sleep Mode Clock Gating Control Register 0
0x110
read-write
n
0x0
0x0
SYSCTL_SCGC0_ADCSPD
ADC Sample Speed
8
10
SYSCTL_SCGC0_ADCSPD125K
125K samples/second
0x0
SYSCTL_SCGC0_ADCSPD250K
250K samples/second
0x1
SYSCTL_SCGC0_ADCSPD500K
500K samples/second
0x2
SYSCTL_SCGC0_CAN0
CAN0 Clock Gating Control
24
25
SYSCTLSCGC1
Sleep Mode Clock Gating Control Register 1
0x114
read-write
n
0x0
0x0
SYSCTL_SCGC1_COMP0
Analog Comparator 0 Clock Gating
24
25
SYSCTL_SCGC1_COMP1
Analog Comparator 1 Clock Gating
25
26
SYSCTL_SCGC1_COMP2
Analog Comparator 2 Clock Gating
26
27
SYSCTL_SCGC1_I2C0
I2C0 Clock Gating Control
12
13
SYSCTL_SCGC1_SSI0
SSI0 Clock Gating Control
4
5
SYSCTL_SCGC1_TIMER0
Timer 0 Clock Gating Control
16
17
SYSCTL_SCGC1_TIMER1
Timer 1 Clock Gating Control
17
18
SYSCTL_SCGC1_TIMER2
Timer 2 Clock Gating Control
18
19
SYSCTL_SCGC1_TIMER3
Timer 3 Clock Gating Control
19
20
SYSCTL_SCGC1_UART0
UART0 Clock Gating Control
0
1
SYSCTLSCGC2
Sleep Mode Clock Gating Control Register 2
0x118
read-write
n
0x0
0x0
SYSCTL_SCGC2_GPIOA
Port A Clock Gating Control
0
1
SYSCTL_SCGC2_GPIOB
Port B Clock Gating Control
1
2
SYSCTL_SCGC2_GPIOC
Port C Clock Gating Control
2
3
SYSCTL_SCGC2_GPIOD
Port D Clock Gating Control
3
4
SYSCTL_SCGC2_GPIOE
Port E Clock Gating Control
4
5
SYSCTL_SCGC2_UDMA
Micro-DMA Clock Gating Control
13
14
SYSCTLSRCR0
Software Reset Control 0
0x40
read-write
n
0x0
0x0
SYSCTL_SRCR0_CAN0
CAN0 Reset Control
24
25
SYSCTLSRCR1
Software Reset Control 1
0x44
read-write
n
0x0
0x0
SYSCTL_SRCR1_COMP0
Analog Comp 0 Reset Control
24
25
SYSCTL_SRCR1_COMP1
Analog Comp 1 Reset Control
25
26
SYSCTL_SRCR1_COMP2
Analog Comp 2 Reset Control
26
27
SYSCTL_SRCR1_I2C0
I2C0 Reset Control
12
13
SYSCTL_SRCR1_SSI0
SSI0 Reset Control
4
5
SYSCTL_SRCR1_TIMER0
Timer 0 Reset Control
16
17
SYSCTL_SRCR1_TIMER1
Timer 1 Reset Control
17
18
SYSCTL_SRCR1_TIMER2
Timer 2 Reset Control
18
19
SYSCTL_SRCR1_TIMER3
Timer 3 Reset Control
19
20
SYSCTL_SRCR1_UART0
UART0 Reset Control
0
1
SYSCTLSRCR2
Software Reset Control 2
0x48
read-write
n
0x0
0x0
SYSCTL_SRCR2_GPIOA
Port A Reset Control
0
1
SYSCTL_SRCR2_GPIOB
Port B Reset Control
1
2
SYSCTL_SRCR2_GPIOC
Port C Reset Control
2
3
SYSCTL_SRCR2_GPIOD
Port D Reset Control
3
4
SYSCTL_SRCR2_GPIOE
Port E Reset Control
4
5
SYSCTL_SRCR2_UDMA
Micro-DMA Reset Control
13
14
TIMER0
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER1
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER2
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER3
Register map for TIMER0 peripheral
TIMER
0x0
0x0
0x1000
registers
n
CFG
GPTM Configuration
0x0
-1
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
CTL
GPTM Control
0xC
-1
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
ICR
GPTM Interrupt Clear
0x24
-1
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
IMR
GPTM Interrupt Mask
0x18
-1
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
MIS
GPTM Masked Interrupt Status
0x20
-1
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
RIS
GPTM Raw Interrupt Status
0x1C
-1
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TAILR
GPTM Timer A Interval Load
0x28
-1
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TAMATCHR
GPTM Timer A Match
0x30
-1
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TAMR
GPTM Timer A Mode
0x4
-1
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TAPR
GPTM Timer A Prescale
0x38
-1
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TAR
GPTM Timer A
0x48
-1
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TBILR
GPTM Timer B Interval Load
0x2C
-1
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TBMATCHR
GPTM Timer B Match
0x34
-1
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TBMR
GPTM Timer B Mode
0x8
-1
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TBPR
GPTM Timer B Prescale
0x3C
-1
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TBR
GPTM Timer B
0x4C
-1
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
TIMER0CFG
GPTM Configuration
0x0
read-write
n
0x0
0x0
TIMER_CFG
GPTM Configuration
0
3
TIMER_CFG_32_BIT_TIMER
32-bit timer configuration
0x0
TIMER_CFG_32_BIT_RTC
32-bit real-time clock (RTC) counter configuration
0x1
TIMER_CFG_16_BIT
16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR
0x4
TIMER0CTL
GPTM Control
0xC
read-write
n
0x0
0x0
TIMER_CTL_RTCEN
GPTM RTC Enable
4
5
TIMER_CTL_TAEN
GPTM Timer A Enable
0
1
TIMER_CTL_TAEVENT
GPTM Timer A Event Mode
2
4
TIMER_CTL_TAEVENT_POS
Positive edge
0x0
TIMER_CTL_TAEVENT_NEG
Negative edge
0x1
TIMER_CTL_TAEVENT_BOTH
Both edges
0x3
TIMER_CTL_TAOTE
GPTM Timer A Output Trigger Enable
5
6
TIMER_CTL_TAPWML
GPTM Timer A PWM Output Level
6
7
TIMER_CTL_TASTALL
GPTM Timer A Stall Enable
1
2
TIMER_CTL_TBEN
GPTM Timer B Enable
8
9
TIMER_CTL_TBEVENT
GPTM Timer B Event Mode
10
12
TIMER_CTL_TBEVENT_POS
Positive edge
0x0
TIMER_CTL_TBEVENT_NEG
Negative edge
0x1
TIMER_CTL_TBEVENT_BOTH
Both edges
0x3
TIMER_CTL_TBOTE
GPTM Timer B Output Trigger Enable
13
14
TIMER_CTL_TBPWML
GPTM Timer B PWM Output Level
14
15
TIMER_CTL_TBSTALL
GPTM Timer B Stall Enable
9
10
TIMER0ICR
GPTM Interrupt Clear
0x24
write-only
n
0x0
0x0
TIMER_ICR_CAECINT
GPTM Capture A Event Interrupt Clear
2
3
write-only
TIMER_ICR_CAMCINT
GPTM Capture A Match Interrupt Clear
1
2
write-only
TIMER_ICR_CBECINT
GPTM Capture B Event Interrupt Clear
10
11
write-only
TIMER_ICR_CBMCINT
GPTM Capture B Match Interrupt Clear
9
10
write-only
TIMER_ICR_RTCCINT
GPTM RTC Interrupt Clear
3
4
write-only
TIMER_ICR_TATOCINT
GPTM Timer A Time-Out Raw Interrupt
0
1
write-only
TIMER_ICR_TBTOCINT
GPTM Timer B Time-Out Interrupt Clear
8
9
write-only
TIMER0IMR
GPTM Interrupt Mask
0x18
read-write
n
0x0
0x0
TIMER_IMR_CAEIM
GPTM Capture A Event Interrupt Mask
2
3
TIMER_IMR_CAMIM
GPTM Capture A Match Interrupt Mask
1
2
TIMER_IMR_CBEIM
GPTM Capture B Event Interrupt Mask
10
11
TIMER_IMR_CBMIM
GPTM Capture B Match Interrupt Mask
9
10
TIMER_IMR_RTCIM
GPTM RTC Interrupt Mask
3
4
TIMER_IMR_TATOIM
GPTM Timer A Time-Out Interrupt Mask
0
1
TIMER_IMR_TBTOIM
GPTM Timer B Time-Out Interrupt Mask
8
9
TIMER0MIS
GPTM Masked Interrupt Status
0x20
read-write
n
0x0
0x0
TIMER_MIS_CAEMIS
GPTM Capture A Event Masked Interrupt
2
3
TIMER_MIS_CAMMIS
GPTM Capture A Match Masked Interrupt
1
2
TIMER_MIS_CBEMIS
GPTM Capture B Event Masked Interrupt
10
11
TIMER_MIS_CBMMIS
GPTM Capture B Match Masked Interrupt
9
10
TIMER_MIS_RTCMIS
GPTM RTC Masked Interrupt
3
4
TIMER_MIS_TATOMIS
GPTM Timer A Time-Out Masked Interrupt
0
1
TIMER_MIS_TBTOMIS
GPTM Timer B Time-Out Masked Interrupt
8
9
TIMER0RIS
GPTM Raw Interrupt Status
0x1C
read-write
n
0x0
0x0
TIMER_RIS_CAERIS
GPTM Capture A Event Raw Interrupt
2
3
TIMER_RIS_CAMRIS
GPTM Capture A Match Raw Interrupt
1
2
TIMER_RIS_CBERIS
GPTM Capture B Event Raw Interrupt
10
11
TIMER_RIS_CBMRIS
GPTM Capture B Match Raw Interrupt
9
10
TIMER_RIS_RTCRIS
GPTM RTC Raw Interrupt
3
4
TIMER_RIS_TATORIS
GPTM Timer A Time-Out Raw Interrupt
0
1
TIMER_RIS_TBTORIS
GPTM Timer B Time-Out Raw Interrupt
8
9
TIMER0TAILR
GPTM Timer A Interval Load
0x28
read-write
n
0x0
0x0
TIMER_TAILR_TAILRH
GPTM Timer A Interval Load Register High
16
32
TIMER_TAILR_TAILRL
GPTM Timer A Interval Load Register Low
0
16
TIMER0TAMATCHR
GPTM Timer A Match
0x30
read-write
n
0x0
0x0
TIMER_TAMATCHR_TAMRH
GPTM Timer A Match Register High
16
32
TIMER_TAMATCHR_TAMRL
GPTM Timer A Match Register Low
0
16
TIMER0TAMR
GPTM Timer A Mode
0x4
read-write
n
0x0
0x0
TIMER_TAMR_TAAMS
GPTM Timer A Alternate Mode Select
3
4
TIMER_TAMR_TACMR
GPTM Timer A Capture Mode
2
3
TIMER_TAMR_TAMR
GPTM Timer A Mode
0
2
TIMER_TAMR_TAMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TAMR_TAMR_PERIOD
Periodic Timer mode
0x2
TIMER_TAMR_TAMR_CAP
Capture mode
0x3
TIMER0TAPR
GPTM Timer A Prescale
0x38
read-write
n
0x0
0x0
TIMER_TAPR_TAPSR
GPTM Timer A Prescale
0
8
TIMER0TAR
GPTM Timer A
0x48
read-write
n
0x0
0x0
TIMER_TAR_TARH
GPTM Timer A Register High
16
32
TIMER_TAR_TARL
GPTM Timer A Register Low
0
16
TIMER0TBILR
GPTM Timer B Interval Load
0x2C
read-write
n
0x0
0x0
TIMER_TBILR_TBILRL
GPTM Timer B Interval Load Register
0
16
TIMER0TBMATCHR
GPTM Timer B Match
0x34
read-write
n
0x0
0x0
TIMER_TBMATCHR_TBMRL
GPTM Timer B Match Register Low
0
16
TIMER0TBMR
GPTM Timer B Mode
0x8
read-write
n
0x0
0x0
TIMER_TBMR_TBAMS
GPTM Timer B Alternate Mode Select
3
4
TIMER_TBMR_TBCMR
GPTM Timer B Capture Mode
2
3
TIMER_TBMR_TBMR
GPTM Timer B Mode
0
2
TIMER_TBMR_TBMR_1_SHOT
One-Shot Timer mode
0x1
TIMER_TBMR_TBMR_PERIOD
Periodic Timer mode
0x2
TIMER_TBMR_TBMR_CAP
Capture mode
0x3
TIMER0TBPR
GPTM Timer B Prescale
0x3C
read-write
n
0x0
0x0
TIMER_TBPR_TBPSR
GPTM Timer B Prescale
0
8
TIMER0TBR
GPTM Timer B
0x4C
read-write
n
0x0
0x0
TIMER_TBR_TBRL
GPTM Timer B
0
16
UART0
Register map for UART0 peripheral
UART
0x0
0x0
0x1000
registers
n
CTL
UART Control
0x30
-1
read-write
n
0x0
0x0
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
DMACTL
UART DMA Control
0x48
-1
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
DR
UART Data
0x0
-1
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
ECR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
FBRD
UART Fractional Baud-Rate Divisor
0x28
-1
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
FR
UART Flag
0x18
-1
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
IBRD
UART Integer Baud-Rate Divisor
0x24
-1
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
ICR
UART Interrupt Clear
0x44
-1
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
IFLS
UART Interrupt FIFO Level Select
0x34
-1
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO and lt = 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO and lt = 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO and lt = 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO and lt = 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO and lt = 7/8 full
0x4
ILPR
UART IrDA Low-Power Register
0x20
-1
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
IM
UART Interrupt Mask
0x38
-1
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
LCRH
UART Line Control
0x2C
-1
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
MIS
UART Masked Interrupt Status
0x40
-1
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
RIS
UART Raw Interrupt Status
0x3C
-1
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
RSR
UART Receive Status/Error Clear
0x4
-1
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UART0CTL
UART Control
0x30
read-write
n
0x0
0x0
UART_CTL_LBE
UART Loop Back Enable
7
8
UART_CTL_RXE
UART Receive Enable
9
10
UART_CTL_SIREN
UART SIR Enable
1
2
UART_CTL_SIRLP
UART SIR Low-Power Mode
2
3
UART_CTL_TXE
UART Transmit Enable
8
9
UART_CTL_UARTEN
UART Enable
0
1
UART0DMACTL
UART DMA Control
0x48
read-write
n
0x0
0x0
UART_DMACTL_DMAERR
DMA on Error
2
3
UART_DMACTL_RXDMAE
Receive DMA Enable
0
1
UART_DMACTL_TXDMAE
Transmit DMA Enable
1
2
UART0DR
UART Data
0x0
read-write
n
0x0
0x0
UART_DR_BE
UART Break Error
10
11
UART_DR_DATA
Data Transmitted or Received
0
8
UART_DR_FE
UART Framing Error
8
9
UART_DR_OE
UART Overrun Error
11
12
UART_DR_PE
UART Parity Error
9
10
UART0ECR
UART Receive Status/Error Clear
UART_ALT
0x4
read-write
n
0x0
0x0
UART_ECR_DATA
Error Clear
0
8
UART0FBRD
UART Fractional Baud-Rate Divisor
0x28
read-write
n
0x0
0x0
UART_FBRD_DIVFRAC
Fractional Baud-Rate Divisor
0
6
UART0FR
UART Flag
0x18
read-write
n
0x0
0x0
UART_FR_BUSY
UART Busy
3
4
UART_FR_RXFE
UART Receive FIFO Empty
4
5
UART_FR_RXFF
UART Receive FIFO Full
6
7
UART_FR_TXFE
UART Transmit FIFO Empty
7
8
UART_FR_TXFF
UART Transmit FIFO Full
5
6
UART0IBRD
UART Integer Baud-Rate Divisor
0x24
read-write
n
0x0
0x0
UART_IBRD_DIVINT
Integer Baud-Rate Divisor
0
16
UART0ICR
UART Interrupt Clear
0x44
write-only
n
0x0
0x0
UART_ICR_BEIC
Break Error Interrupt Clear
9
10
write-only
UART_ICR_FEIC
Framing Error Interrupt Clear
7
8
write-only
UART_ICR_OEIC
Overrun Error Interrupt Clear
10
11
write-only
UART_ICR_PEIC
Parity Error Interrupt Clear
8
9
write-only
UART_ICR_RTIC
Receive Time-Out Interrupt Clear
6
7
write-only
UART_ICR_RXIC
Receive Interrupt Clear
4
5
write-only
UART_ICR_TXIC
Transmit Interrupt Clear
5
6
write-only
UART0IFLS
UART Interrupt FIFO Level Select
0x34
read-write
n
0x0
0x0
UART_IFLS_RX
UART Receive Interrupt FIFO Level Select
3
6
UART_IFLS_RX1_8
RX FIFO >= 1/8 full
0x0
UART_IFLS_RX2_8
RX FIFO >= 1/4 full
0x1
UART_IFLS_RX4_8
RX FIFO >= 1/2 full (default)
0x2
UART_IFLS_RX6_8
RX FIFO >= 3/4 full
0x3
UART_IFLS_RX7_8
RX FIFO >= 7/8 full
0x4
UART_IFLS_TX
UART Transmit Interrupt FIFO Level Select
0
3
UART_IFLS_TX1_8
TX FIFO <= 1/8 full
0x0
UART_IFLS_TX2_8
TX FIFO <= 1/4 full
0x1
UART_IFLS_TX4_8
TX FIFO <= 1/2 full (default)
0x2
UART_IFLS_TX6_8
TX FIFO <= 3/4 full
0x3
UART_IFLS_TX7_8
TX FIFO <= 7/8 full
0x4
UART0ILPR
UART IrDA Low-Power Register
0x20
read-write
n
0x0
0x0
UART_ILPR_ILPDVSR
IrDA Low-Power Divisor
0
8
UART0IM
UART Interrupt Mask
0x38
read-write
n
0x0
0x0
UART_IM_BEIM
UART Break Error Interrupt Mask
9
10
UART_IM_FEIM
UART Framing Error Interrupt Mask
7
8
UART_IM_OEIM
UART Overrun Error Interrupt Mask
10
11
UART_IM_PEIM
UART Parity Error Interrupt Mask
8
9
UART_IM_RTIM
UART Receive Time-Out Interrupt Mask
6
7
UART_IM_RXIM
UART Receive Interrupt Mask
4
5
UART_IM_TXIM
UART Transmit Interrupt Mask
5
6
UART0LCRH
UART Line Control
0x2C
read-write
n
0x0
0x0
UART_LCRH_BRK
UART Send Break
0
1
UART_LCRH_EPS
UART Even Parity Select
2
3
UART_LCRH_FEN
UART Enable FIFOs
4
5
UART_LCRH_PEN
UART Parity Enable
1
2
UART_LCRH_SPS
UART Stick Parity Select
7
8
UART_LCRH_STP2
UART Two Stop Bits Select
3
4
UART_LCRH_WLEN
UART Word Length
5
7
UART_LCRH_WLEN_5
5 bits (default)
0x0
UART_LCRH_WLEN_6
6 bits
0x1
UART_LCRH_WLEN_7
7 bits
0x2
UART_LCRH_WLEN_8
8 bits
0x3
UART0MIS
UART Masked Interrupt Status
0x40
read-write
n
0x0
0x0
UART_MIS_BEMIS
UART Break Error Masked Interrupt Status
9
10
UART_MIS_FEMIS
UART Framing Error Masked Interrupt Status
7
8
UART_MIS_OEMIS
UART Overrun Error Masked Interrupt Status
10
11
UART_MIS_PEMIS
UART Parity Error Masked Interrupt Status
8
9
UART_MIS_RTMIS
UART Receive Time-Out Masked Interrupt Status
6
7
UART_MIS_RXMIS
UART Receive Masked Interrupt Status
4
5
UART_MIS_TXMIS
UART Transmit Masked Interrupt Status
5
6
UART0RIS
UART Raw Interrupt Status
0x3C
read-write
n
0x0
0x0
UART_RIS_BERIS
UART Break Error Raw Interrupt Status
9
10
UART_RIS_FERIS
UART Framing Error Raw Interrupt Status
7
8
UART_RIS_OERIS
UART Overrun Error Raw Interrupt Status
10
11
UART_RIS_PERIS
UART Parity Error Raw Interrupt Status
8
9
UART_RIS_RTRIS
UART Receive Time-Out Raw Interrupt Status
6
7
UART_RIS_RXRIS
UART Receive Raw Interrupt Status
4
5
UART_RIS_TXRIS
UART Transmit Raw Interrupt Status
5
6
UART0RSR
UART Receive Status/Error Clear
0x4
read-write
n
0x0
0x0
UART_RSR_BE
UART Break Error
2
3
UART_RSR_FE
UART Framing Error
0
1
UART_RSR_OE
UART Overrun Error
3
4
UART_RSR_PE
UART Parity Error
1
2
UDMA
Register map for UDMA peripheral
UDM
0x0
0x0
0x1000
registers
n
ALTBASE
DMA Alternate Channel Control Base Pointer
0xC
-1
read-write
n
0x0
0x0
UDMA_ALTBASE_ADDR
Alternate Channel Address Pointer
0
32
ALTCLR
DMA Channel Primary Alternate Clear
0x34
-1
write-only
n
0x0
0x0
UDMA_ALTCLR_CLR
Channel [n] Alternate Clear
0
32
write-only
ALTSET
DMA Channel Primary Alternate Set
0x30
-1
read-write
n
0x0
0x0
UDMA_ALTSET_SET
Channel [n] Alternate Set
0
32
CFG
DMA Configuration
0x4
-1
write-only
n
0x0
0x0
UDMA_CFG_MASTEN
Controller Master Enable
0
1
write-only
CTLBASE
DMA Channel Control Base Pointer
0x8
-1
read-write
n
0x0
0x0
UDMA_CTLBASE_ADDR
Channel Control Base Address
10
32
ENACLR
DMA Channel Enable Clear
0x2C
-1
write-only
n
0x0
0x0
UDMA_ENACLR_CLR
Clear Channel [n] Enable Clear
0
32
write-only
ENASET
DMA Channel Enable Set
0x28
-1
read-write
n
0x0
0x0
UDMA_ENASET_SET
Channel [n] Enable Set
0
32
ERRCLR
DMA Bus Error Clear
0x4C
-1
read-write
n
0x0
0x0
UDMA_ERRCLR_ERRCLR
uDMA Bus Error Status
0
1
PRIOCLR
DMA Channel Priority Clear
0x3C
-1
write-only
n
0x0
0x0
UDMA_PRIOCLR_CLR
Channel [n] Priority Clear
0
32
write-only
PRIOSET
DMA Channel Priority Set
0x38
-1
read-write
n
0x0
0x0
UDMA_PRIOSET_SET
Channel [n] Priority Set
0
32
REQMASKCLR
DMA Channel Request Mask Clear
0x24
-1
write-only
n
0x0
0x0
UDMA_REQMASKCLR_CLR
Channel [n] Request Mask Clear
0
32
write-only
REQMASKSET
DMA Channel Request Mask Set
0x20
-1
read-write
n
0x0
0x0
UDMA_REQMASKSET_SET
Channel [n] Request Mask Set
0
32
STAT
DMA Status
0x0
-1
read-write
n
0x0
0x0
UDMA_STAT_DMACHANS
Available uDMA Channels Minus 1
16
21
UDMA_STAT_MASTEN
Master Enable Status
0
1
UDMA_STAT_STATE
Control State Machine Status
4
8
UDMA_STAT_STATE_IDLE
Idle
0x0
UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x1
UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x2
UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x3
UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x4
UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x5
UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x6
UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x7
UDMA_STAT_STATE_STALL
Stalled
0x8
UDMA_STAT_STATE_DONE
Done
0x9
UDMA_STAT_STATE_UNDEF
Undefined
0xa
SWREQ
DMA Channel Software Request
0x14
-1
write-only
n
0x0
0x0
UDMA_SWREQ
Channel [n] Software Request
0
32
write-only
UDMAALTBASE
DMA Alternate Channel Control Base Pointer
0xC
read-write
n
0x0
0x0
UDMA_ALTBASE_ADDR
Alternate Channel Address Pointer
0
32
UDMAALTCLR
DMA Channel Primary Alternate Clear
0x34
write-only
n
0x0
0x0
UDMA_ALTCLR_CLR
Channel [n] Alternate Clear
0
32
write-only
UDMAALTSET
DMA Channel Primary Alternate Set
0x30
read-write
n
0x0
0x0
UDMA_ALTSET_SET
Channel [n] Alternate Set
0
32
UDMACFG
DMA Configuration
0x4
write-only
n
0x0
0x0
UDMA_CFG_MASTEN
Controller Master Enable
0
1
write-only
UDMACTLBASE
DMA Channel Control Base Pointer
0x8
read-write
n
0x0
0x0
UDMA_CTLBASE_ADDR
Channel Control Base Address
10
32
UDMAENACLR
DMA Channel Enable Clear
0x2C
write-only
n
0x0
0x0
UDMA_ENACLR_CLR
Clear Channel [n] Enable Clear
0
32
write-only
UDMAENASET
DMA Channel Enable Set
0x28
read-write
n
0x0
0x0
UDMA_ENASET_SET
Channel [n] Enable Set
0
32
UDMAERRCLR
DMA Bus Error Clear
0x4C
read-write
n
0x0
0x0
UDMA_ERRCLR_ERRCLR
uDMA Bus Error Status
0
1
UDMAPRIOCLR
DMA Channel Priority Clear
0x3C
write-only
n
0x0
0x0
UDMA_PRIOCLR_CLR
Channel [n] Priority Clear
0
32
write-only
UDMAPRIOSET
DMA Channel Priority Set
0x38
read-write
n
0x0
0x0
UDMA_PRIOSET_SET
Channel [n] Priority Set
0
32
UDMAREQMASKCLR
DMA Channel Request Mask Clear
0x24
write-only
n
0x0
0x0
UDMA_REQMASKCLR_CLR
Channel [n] Request Mask Clear
0
32
write-only
UDMAREQMASKSET
DMA Channel Request Mask Set
0x20
read-write
n
0x0
0x0
UDMA_REQMASKSET_SET
Channel [n] Request Mask Set
0
32
UDMASTAT
DMA Status
0x0
read-write
n
0x0
0x0
UDMA_STAT_DMACHANS
Available uDMA Channels Minus 1
16
21
UDMA_STAT_MASTEN
Master Enable Status
0
1
UDMA_STAT_STATE
Control State Machine Status
4
8
UDMA_STAT_STATE_IDLE
Idle
0x0
UDMA_STAT_STATE_RD_CTRL
Reading channel controller data
0x1
UDMA_STAT_STATE_RD_SRCENDP
Reading source end pointer
0x2
UDMA_STAT_STATE_RD_DSTENDP
Reading destination end pointer
0x3
UDMA_STAT_STATE_RD_SRCDAT
Reading source data
0x4
UDMA_STAT_STATE_WR_DSTDAT
Writing destination data
0x5
UDMA_STAT_STATE_WAIT
Waiting for uDMA request to clear
0x6
UDMA_STAT_STATE_WR_CTRL
Writing channel controller data
0x7
UDMA_STAT_STATE_STALL
Stalled
0x8
UDMA_STAT_STATE_DONE
Done
0x9
UDMA_STAT_STATE_UNDEF
Undefined
0xa
UDMASWREQ
DMA Channel Software Request
0x14
write-only
n
0x0
0x0
UDMA_SWREQ
Channel [n] Software Request
0
32
write-only
UDMAUSEBURSTCLR
DMA Channel Useburst Clear
0x1C
write-only
n
0x0
0x0
UDMA_USEBURSTCLR_CLR
Channel [n] Useburst Clear
0
32
write-only
UDMAUSEBURSTSET
DMA Channel Useburst Set
0x18
read-write
n
0x0
0x0
UDMA_USEBURSTSET_SET
Channel [n] Useburst Set
0
32
UDMAWAITSTAT
DMA Channel Wait-on-Request Status
0x10
read-write
n
0x0
0x0
UDMA_WAITSTAT_WAITREQ
Channel [n] Wait Status
0
32
USEBURSTCLR
DMA Channel Useburst Clear
0x1C
-1
write-only
n
0x0
0x0
UDMA_USEBURSTCLR_CLR
Channel [n] Useburst Clear
0
32
write-only
USEBURSTSET
DMA Channel Useburst Set
0x18
-1
read-write
n
0x0
0x0
UDMA_USEBURSTSET_SET
Channel [n] Useburst Set
0
32
WAITSTAT
DMA Channel Wait-on-Request Status
0x10
-1
read-write
n
0x0
0x0
UDMA_WAITSTAT_WAITREQ
Channel [n] Wait Status
0
32
WATCHDOG0
Register map for WATCHDOG0 peripheral
WATCHDOG
0x0
0x0
0x1000
registers
n
CTL
Watchdog Control
0x8
-1
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
ICR
Watchdog Interrupt Clear
0xC
-1
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
LOAD
Watchdog Load
0x0
-1
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
LOCK
Watchdog Lock
0xC00
-1
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
WDT_LOCK_UNLOCK
Unlocks the watchdog timer
0x1acce551
MIS
Watchdog Masked Interrupt Status
0x14
-1
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
RIS
Watchdog Raw Interrupt Status
0x10
-1
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
TEST
Watchdog Test
0x418
-1
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
VALUE
Watchdog Value
0x4
-1
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32
WATCHDOG0CTL
Watchdog Control
0x8
read-write
n
0x0
0x0
WDT_CTL_INTEN
Watchdog Interrupt Enable
0
1
WDT_CTL_RESEN
Watchdog Reset Enable
1
2
WATCHDOG0ICR
Watchdog Interrupt Clear
0xC
write-only
n
0x0
0x0
WDT_ICR
Watchdog Interrupt Clear
0
32
write-only
WATCHDOG0LOAD
Watchdog Load
0x0
read-write
n
0x0
0x0
WDT_LOAD
Watchdog Load Value
0
32
WATCHDOG0LOCK
Watchdog Lock
0xC00
read-write
n
0x0
0x0
WDT_LOCK
Watchdog Lock
0
32
WDT_LOCK_UNLOCKED
Unlocked
0x0
WDT_LOCK_LOCKED
Locked
0x1
WDT_LOCK_UNLOCK
Unlocks the watchdog timer
0x1acce551
WATCHDOG0MIS
Watchdog Masked Interrupt Status
0x14
read-write
n
0x0
0x0
WDT_MIS_WDTMIS
Watchdog Masked Interrupt Status
0
1
WATCHDOG0RIS
Watchdog Raw Interrupt Status
0x10
read-write
n
0x0
0x0
WDT_RIS_WDTRIS
Watchdog Raw Interrupt Status
0
1
WATCHDOG0TEST
Watchdog Test
0x418
read-write
n
0x0
0x0
WDT_TEST_STALL
Watchdog Stall Enable
8
9
WATCHDOG0VALUE
Watchdog Value
0x4
read-write
n
0x0
0x0
WDT_VALUE
Watchdog Value
0
32